AMD to start 45nm ramp in H1 2008

[red]

In light of the delay and the higher-than-expected TDP values, the motherboard makers expressed concerns about AMD's planned migration to 45nm production in 2008 with the possibility that the Socket AM3 CPU lineup, including Deneb FX, Deneb, Propus, Regor and Sargas, may all have their launch schedules postponed.

- Digitimes

Why is this a sticky anyway? It's not likely considering AMD's execution nor is it a product anyhow.

[BrowncoatGR]

Must concur with this!

Didn't see such a constructive post in News section for a long time!

On this, I guess that AMD invested heavily in SOI tech improving it with DSL, and SiGe and they'll go with it in 45nm era inventing something that'll further extend performance scaling… but 45nm does look like wall for SOI, that has served quite well (who would imagine that dual core K8 would reach beyond 3.2 GHz when single core Winchester was introduced?)

Afaik AMD is not using SiGe yet. Do you have any info proving otherwise? In fact im speculating that they might be aiming to use it a 45nm now.

[Shintai]

Afaik AMD is not using SiGe yet. Do you have any info proving otherwise? In fact im speculating that they might be aiming to use it a 45nm now.

They already use SiGe, so does IBM.

http://www.amd.com/us-en/Corporate/V...103048,00.html

[BrowncoatGR]

Uhm no not for brisbane

Semiconductor Insights (SI), a leading technical advisor to the global microelectronics industry recently performed an analysis on the 65nm AMD Athlon 64 X2 dual-core desktop processor. Upon completion of the analysis, Semiconductor Insights awarded AMD with their 2006 INSIGHT Award for Most Innovative Process Technology.

“Our analysis of the device has confirmed that the 65nm AMD Athlon 64 X2 dual-core processor, produced at AMD Fab 36, uses minimum gate lengths of 35nm, nine copper and one aluminum metal levels, strained silicon channel and a Silicon on Insulator (SOI) substrate,” said Don Scansen, lead process analyst at Semiconductor Insights. “Put altogether, it is an impressive technology package”

http://www.amd.com/us-en/Corporate/V...114609,00.html
but according to this they are using it for 10h Opterons
http://www.amd.com/us-en/Corporate/V..._15275,00.html

# The first Quad-Core AMD Opteron processors will be produced with AMD’s fourth generation, most advanced 65nm process, which includes the latest strained silicon engineering to act as a key enabler of improved performance-per-watt. Specific process technologies include:

* Silicon-on-insulator (SOI) process lowers power consumption and improves performance
* Dual-stress liner (DSL) technology increases transistor performance, while controlling power consumption and heat dissipation
* Embedded silicon germanium (e-SiGe) delivers a 40 percent potential increase in transistor performance, reduced power consumption and heat dissipation, and high product yields

[Shintai]

Uhm no not for brisbane http://www.amd.com/us-en/Corporate/V...114609,00.html
but according to this they are using it for 10h Opterons
http://www.amd.com/us-en/Corporate/V..._15275,00.html

It would be quite odd if they used difference techniques on the same production facility.

Anyway, you proved yourself they use it on 65nm.

http://news.zdnet.co.uk/hardware/0,1...9284991,00.htm

They even use it on 90nm. But there is different ways to use it.

But everyone with strained silicon uses SiGe.

[BrowncoatGR]

Seems you are right about 65nm http://www.eetimes.com/showArticle.j...leID=196701745

[Shintai]

Seems you are right about 65nm http://www.eetimes.com/showArticle.j...leID=196701745

I´m also right about 90nm for that matter. Everything that is strained is SiGe.

[BrowncoatGR]

Yes agreed

[flopper]

so AMD "is" screwed then.
Until they get a better technology out to make transistors work as they want them to.
Can they survive that long?

[verndewd]

I wonder about AMD e SiGe; jack did some research and found there wasnt much to speak of on brisbane, set that aside and its still a strain engineering question when did we see an actual 40 % jump in the perf of transistors?

There are holes there that need filling. pun not intended.

[JumpingJack]

Seems you are right about 65nm http://www.eetimes.com/showArticle.j...leID=196701745

This is is a better reference:
http://www.eetimes.com/showArticle.j...leID=197003451

Page 2.



Let me see if I can describe where the SiGe is in this picture... (since it is copyrighted I cannot 'edit/draw' on it and repost it ) ....

There is a dark dot at the top of the 'apex' buried under the slightly darker gray overlayer right on top of the transistors. Ok, that is the NiSi that helps with the contact resistance. Down below that dot and making up a lighter column is the poly-si gate electrode, follow that column of slighty 'lighter' contrast of the poly-si electrode to the point where it contacts the substrate (those rolling looking hills at the bottom).

At that junction where the poly meets those 'hills' is the gate oxide (the resolution and size of this image makes it impossible to see the gate oxide, it is ultra thin). Go down into the hill about 1/3 of the way and look on either side where the area is slightly darker (for example, just above the 'M' in 'AMD' or just above the 'y' in the word 'layer' of the picture, as an example), you can see that each transistor has these to 'corner-like' darkened regions on either side of the gate electrode just beneath the silicon substrate .. this is the SiGe.

Jack

[JumpingJack]

so AMD "is" screwed then.
Until they get a better technology out to make transistors work as they want them to.
Can they survive that long?

Yeah, sorta ... it get's worse. For barcelona, AMD thickened up the gate oxide because of leakage problems (by about 25&#37, what this does is ruins the transistor switching speed.

This is harder to prove -- http://www.eetimes.com/showArticle.j...leID=202100946

AMD's brisbane/65 nm process had exactly the same gate oxide thickness as Intel's -- see (unlinkable) IEDM 2005 proceedings, AMD's 65 nm process paper (sorry, need to use a library for that one )...

So by thickening it up, they are trying to bring down gate leakage, but it is not going well by the looks of it.... Phenom at 2.4 Ghz is 125 Watts TDP... ouch. (BTW, you can email J. Boyd -- email in the article and ask if they thickened up, he will respond kindly as he did me )

[verndewd]

you should post a penryn cross section, jack. Well maybe not we wouldnt want a riot at the AMD gates. (joking)

[Shadowmage]

Yeah, sorta ... it get's worse. For barcelona, AMD thickened up the gate oxide because of leakage problems (by about 25%), what this does is ruins the transistor switching speed.

This is harder to prove -- http://www.eetimes.com/showArticle.j...leID=202100946

AMD's brisbane/65 nm process had exactly the same gate oxide thickness as Intel's -- see (unlinkable) IEDM 2005 proceedings, AMD's 65 nm process paper (sorry, need to use a library for that one )...

So by thickening it up, they are trying to bring down gate leakage, but it is not going well by the looks of it.... Phenom at 2.4 Ghz is 125 Watts TDP... ouch. (BTW, you can email J. Boyd -- email in the article and ask if they thickened up, he will respond kindly as he did me )

It's true they have a thicker gate oxide, but their V_t is also much lower to compensate, according to the article.

[BrowncoatGR]

This is is a better reference:
http://www.eetimes.com/showArticle.j...leID=197003451

Page 2.



Let me see if I can describe where the SiGe is in this picture... (since it is copyrighted I cannot 'edit/draw' on it and repost it ) ....

There is a dark dot at the top of the 'apex' buried under the slightly darker gray overlayer right on top of the transistors. Ok, that is the NiSi that helps with the contact resistance. Down below that dot and making up a lighter column is the poly-si gate electrode, follow that column of slighty 'lighter' contrast of the poly-si electrode to the point where it contacts the substrate (those rolling looking hills at the bottom).

At that junction where the poly meets those 'hills' is the gate oxide (the resolution and size of this image makes it impossible to see the gate oxide, it is ultra thin). Go down into the hill about 1/3 of the way and look on either side where the area is slightly darker (for example, just above the 'M' in 'AMD' or just above the 'y' in the word 'layer' of the picture, as an example), you can see that each transistor has these to 'corner-like' darkened regions on either side of the gate electrode just beneath the silicon substrate .. this is the SiGe.

Jack

Thanks. Interesting stuff. I'm a bit confused though now. What exactly is the difference between SGOI and SSOI, if any?

[verndewd]

i just read about this,,,, forgot it al !! stupid embedded memory.

ok wait sgoi silicon germanium on insulator
ssoi strained silicon on insulator

From what I have read it seems to be a choice of how one refers to it more than an actual physical difference. I could be wrong but thats exactly waht I recently read.

[RedBull78]

It is rather funny how at first noone cared about the die size process of a cpu but only the overall performance. Thermals by shrinking the die has been very up to attention for both intel and amd and now we're seeing another inside battle who actually leads in silicon transition process.

When will it stop?

I rather see this entire technology under ground and start something new. I wonder if cpu's will require gas to run in near future.

[JumpingJack]

Thanks. Interesting stuff. I'm a bit confused though now. What exactly is the difference between SGOI and SSOI, if any?

SGOI is strained Germanium on Insulator. SSOI is strained silicon on insulator ...

SGOI will be interesting if IBM ever gets it to work... I need to go back and look at the tables, but I think electron mobility in Ge is higher than Si but hole mobility is lower... hmmmmm

EDIT: Check that, electron and hole mobility are both higher in Ge.

Jack

[JumpingJack]

It's true they have a thicker gate oxide, but their V_t is also much lower to compensate, according to the article.

It is all relative, he did not quote a number in the article.... and while Vt is a critical transistor parameter related to performance, saturated drive currents are also a factor (the generally track each other but not necessarily).

Honestly, I cannot comment on absolutes of AMD's process because any published process data is now 2 yrs old, and it has changed a lot by now....

This is why I generalized, thickening up the gate is generally poorer for performance... and as Boyd said, AMD was looking for other ways... finding a way to lower Vt certainly could be one of them, but how much lower they would need to make get Vt to make up the difference is not clear to me.

[zabomb4163]

JumpingJack, i assume you are no lay person in regards to microprocessor technology. May I ask what companies you are affiliated with?

[Zytek_Fan]

The only thing that can save AMD at this point is 45nm K10. Their stock is worth half as much as it was last year, and things still aren't looking good...

[JumpingJack]

JumpingJack, i assume you are no lay person in regards to microprocessor technology. May I ask what companies you are affiliated with?

You may ask ...

I work for a private R&D firm as a staff senior scientist, i.e. we contract out 'slave' R&D labor so to speak. Well, not quite that. Some companies run into tough problems that requires a short burst of R&D effort, however, those problems are few between or are not numerous enough to justify implementing a full R&D staff and associated equipment. So they hand us a problem (and money) to answer very specific questions for them.

My background rests with advanced degrees in chemistry and physics. One dissertation involved studying the gas/solid interfacial surface chemistry of small molecules on Si(100) -- the technologically relevant surface of silicon. I also did some optical studies with Ge on Si(100) and SiGe heterostructures. In fact, I got my degrees at UT Austin, and some of my interactions included working with AMD staff scientist and Motorola staff scientists/engineers. I even took a senior level EE course (not fun -- meaning difficult) from the professor who authors pretty much the standard text on VLSI CMOS devices (Ben Streetman), this is really where I learned alot of the basics.

While working through graduate school I had thought about a career in the microelectronics, but the way it panned out -- nah... I get paid nicely for what I do and the hours are not horrid, I do have a few friends (long lost touch with) that did wind up in smaller companies -- Triquent is one.

Anyway, computer building, playing around, studying has been my hobby for the better part of 16 (check that 18, darn I am getting old) years, with all this high octane education, and since my job requires the better part of 20+ hours per week in libraries searching for would be answers ... I find time to also catch the technical engineering literature on these topics or professional magazines which publish things like 'ooooh, look how cool this could revolutionize the industry', which never pan out.

If you are interested in learning more about the way these wonderful devices are made -- I do suggest Ben Streetman's book "Solid State Electronic Devices" ... it is a Senior/1st yr graduate student level book but goes through most of the basic processing concepts as well as most of the fundamental device physics.

[RedBull78]

You may ask ...

I work for a private R&D firm as a staff senior scientist, i.e. we contract out 'slave' R&D labor so to speak. Well, not quite that. Some companies run into tough problems that requires a short burst of R&D effort, however, those problems are few between or are not numerous enough to justify implementing a full R&D staff and associated equipment. So they hand us a problem (and money) to answer very specific questions for them.

My background rests with advanced degrees in chemistry and physics. One dissertation involved studying the gas/solid interfacial surface chemistry of small molecules on Si(100) -- the technologically relevant surface of silicon. I also did some optical studies with Ge on Si(100) and SiGe heterostructures. In fact, I got my degrees at UT Austin, and some of my interactions included working with AMD staff scientist and Motorola staff scientists/engineers. I even took an senior level EE course (not fun) from the professor who authors pretty much the standard text on VLSI CMOS devices (Ben Streetman), this is really where I learned alot of the basics.

While working through graduate school I had thought about a career in the microelectronics, but the way it panned out -- nah... I get paid nicely for what I do and the hours are not horrid, I do have a few friends (long lost touch with) that did wind up in smaller companies -- Triquent is one.

Anyway, computer building, playing around, studying has been my hobby for the better part of 16 (check that 18, darn I am getting old) years, with all this high octane education, and since my job requires the better part of 20+ hours per week in libraries searching for would be answers ... I find time to also catch the technical engineering literature on these topics or professional magazines which publish things like 'ooooh, look how cool this could revolutionize the industry', which never pan out.

If you are interested in learning more about the way these wonderful devices are made -- I do suggest Ben Streetman's book "Solid State Electronic Devices" ... it is a Senior/1st yr graduate student level book but goes through most of the basic processing concepts as well as most of the fundamental device physics.

I wouldn't mess with you. haha

I hope you get abducted by aliens and bring us some hybrid cpus.

[JumpingJack]

I wouldn't mess with you. haha

I hope you get abducted by aliens and bring us some hybrid cpus.

Meh... I am typical computer geek, just like most everyone here. Argue with me ( or flame away) I don't care

[JumpingJack]

The only thing that can save AMD at this point is 45nm K10. Their stock is worth half as much as it was last year, and things still aren't looking good...

I am not so sure.... I think any reasonable person would conclude they are in deep trouble right now. But I don't think the industry in general will allow them to sink. Money, from somewhere, will arrive to keep them going until the sun rises to brighter days.

Why do I say this ... the big guys -- Dell, HP, Acer, Toshiba etc... have all gotten a taste of what can be had playing these two guys off one another. I think the major OEMs will, if anything, provide them with patronage to keep them going.... which is why I suspect AMD will see some market share gains in Q4.

However, these same OEMs are milking AMD for all they are worth frankly. ASPs for AMD have fallen below the $70 level, and those prices you see on AMD's price list web site are not what the OEMs pay for them, far from it.

AMD does need to get costs under control, and regain some pricing leverage against Intel (this comes with performance, because ultimately, performance is what sells).

My 2 cents.