AMD to start 45nm ramp in H1 2008

[PhilDoc]

Still sure about that ?

http://www.xtremesystems.org/forums/...d.php?t=163780

When you need >1.53V to get to 3GHz while a K8 on 65/90nm does it at under 1.4V , allow me to take your claim with a healthy dose of salt.

What are we talking about, the results of one cpu. Why don't we just wait until we have a few more to look at.

[Face]

More from Xbit:

Chartered May Start Making AMD Processors Using 45nm Process Tech in 2009

Chartered Preps to Manufacture 45nm Microprocessors for AMD

As Advanced Micro Devices is getting ready to start pilot production ramp of its 45nm process technology, its “flexible” manufacturing partner Chartered Semiconductor claims that it would be ready with its 45nm process technology late this year. The contract maker claims that it expects to produce 45nm silicon-on-insulator (SOI) chips by mid-2009, just a little later compared to AMD itself.

“Our 45nm technology bring up is on track. I have also talked in the past that from the industry adoption and ramp standpoint, we should [hardly] see any meaningful volume until probably [the] early part of mid-2009, which roughly [is similar with the ramp of 65nm process technology],” Mr. Hwee said.

Despite of the fact that AMD uses SOI, it will be able to take advantage of Chartered production capacities in the first half of 2009, just like other customers of the Singapore-based contract chipmaker.

“Specifically on the SOI, we do not see any change in terms of the timing as well. It’s going to be around [for production] in that kind of timeframe in the late first half of 2009,” Mr. Hwee added.

Typically contract semiconductor manufactures, such as Chartered or TSMC, first develop their bulk process technologies and then supply their partners so-called libraries of elements and general design rules. Intellectual property owners have to develop their chipsets according to guidelines of the new process technologies; therefore, there is a timeframe between availability of fabrication technologies and volume manufacturing.

X-Bit labs

[bedlamite]

So, no metal gates in AMD's 45 nm?
Interesting.

[BrowncoatGR]

So, no metal gates in AMD's 45 nm?
Interesting.

Well they are not, at least initially. How did you reach that conclusion from this article though? Just to make it cler Chartered ispart of the AMD/IBM alliance.

[bedlamite]

Well, Intel uses mysterious High-k Insulators to cooperate with their metal gates.
AMD still wants to use SOI, so i think they wont use metal gate.
Or im wrong and they have some way to make both.

[BrowncoatGR]

Well, Intel uses mysterious High-k Insulators to cooperate with their metal gates.
AMD still wants to use SOI, so i think they wont use metal gate.
Or im wrong and they have some way to make both.

Thats what they claim although initially they wont use either. Apparently its stilll under development to appear later on 45nm. I guess if they cant make it work they'll be forced to switch to bulk for 32nm.

[verndewd]

Low k is planned for AMD 45nm.

[bedlamite]

Any source of that?
And how they want to make high k + SOI ?

[verndewd]

lol, All the sources are in threads here That I and other posted. Also low k is mentioned for 45nm in alot of amd news briefs. I hope youll excuse moi if I dont rush out and get those for you. When you find the news youll note that its Low k not air gap or ULK/Cu.

Also it could be on my news blog.

http://www.dewdnews.com/

Well, Intel uses mysterious High-k Insulators to cooperate with their metal gates.
AMD still wants to use SOI, so i think they wont use metal gate.
Or im wrong and they have some way to make both.

Mysterious? What would hafnium be then? The only mystery is the alloys and process to make it cohesive and non destructive(so to speak)

The mystery meat I am most interested in is the metal gate alloy. Hafnium aluminum insulation, woot yay , Are the gates platinum/Ra , Now there is a mystery. For some tidbits check out IEEE spectrum october issue.

[DAN16]

[LowRun]

Welcome to the XS forums

[bedlamite]

Well, sorry, but i don't understand all of this technical english so i could miss that.
But thx for correction.

[verndewd]

No problem. In the october issue of IEEE spectrum High K is mentioned. Now grose is in the news with talking about High K for AMD... link
http://www.semiconductor.net/?reques...l&referer_url=

I vote doug as the next AMD ceo. His credentials are Impressive.

[nemrod]

Well, Intel uses mysterious High-k Insulators to cooperate with their metal gates.

No mysterious High-k this is hafnium which was already discuss in itrs 1999
"Gate materials, high-k dielectrics, and capacitors

The challenges and options for high-k dielectrics and the related gate and capacitor processes are many, and there is still considerable debate about the various solutions. One point of agreement is the need for process integration and cooperation. One technical trend where there seems to be agreement is in the need to shift from silicon-insulator-silicon structures to metal-insulator-metal structures. Much of the current work is focused here.

IMEC's approach is an indication of the magnitude of the task of developing gate dielectrics. Marc Heyns, department director of IMEC's Advanced Surface Preparation, Thin Film, ES&H, and Gate Stack organization, reports, "Currently, there is no consensus on the material that can be used as alternative gate dielectric. Development in such a critical layer in an IC is only possible through large-scale international collaboration. That is why we have set up an Industrial Affiliation Program to develop gate dielectrics and gate electrodes (including metal gates) for sub-100nm devices. Within this program, IMEC wants to develop a manufacturable process for thin films (equivalent oxide thickness [EOT] <1.5nm) with low defect density and accurate thickness control. The gate stack must be integrated in the (n and p) MOS transistor, with the possibility to down-scale the stack to 0.5nm EOT." Their work points to ALCVD as the solution. Heyns adds, "ALCVD results in perfect thickness and uniformity, as well as composition control over large substrates. Therefore, we aim to use this technique to deposit very thin, high-k dielectric layers such as (but not limited to) Al2O3, ZrO2, HfO2, and their silicates for use as alternative gate dielectrics.""

[Donnie27]

Originally Posted by Donnie27
AMD is nowhere near 45nm=P
LOL!

[Periander6]

Why is this even a sticky? We basically have zero information about how AMD's 45nm process development is going beyond the equivalent of the "Barcelona is on track" we heard for over a year and that meant absolutely nothing.

[freeloader]

Just imagine for one minute if AMD didn't purchase ATI. They could've possibly used the money they had banked to fund R&D in 45nm and beyond. Just maybe, they would be able to put out 45nm chips in 2008.

[JumpingJack]

Hmm.
Are CPU transistors realy so different from GPU ones?
New Radeons 38x0 will be 55 nm.
Isnt it at least a bit simmilar?

Yes, in fact they are. GPUs are simply many many many watered down FPU units working in parallel, GPUs are highly specialized for one type of application. They are built for parallel number crunching with extra high throughput, but not necessarily clock speed. Thus, the max clocking capability of the GPU does not carry the same kind of emphasis as the general performance of the CPU.

A transistor is a transistor, in the application of a binary on or off, this is where they are similar.... beyond that, they are constructed quite differently.

Jack

[gillll]

well it's not like that u can reverse the merge........

AMD will have to be bold this year and choose a path.

[JumpingJack]

Well, Intel uses mysterious High-k Insulators to cooperate with their metal gates.
AMD still wants to use SOI, so i think they wont use metal gate.
Or im wrong and they have some way to make both.

Well, you are a little confused on your process technology based on the context of this post.

SOI is a substrate, which buries a layer of SiO2 beneath the transistor body. The purpose is to provide perfect electrical isolation from the transistor to the bulk of the rest of the substrate, and isolate each transistor from the other. In non-SOI constructed devices, also called bulk (i.e. no buried SiO2 layer), the electrical isolation is created by what is called a retrograde well implant. What this does is forms a PN junction diode that under normal operations will be reverse biased, as such current will not flow. Both the SOI isolation and the retrograde implant wells leak, but SOI leaks less than the the bulk. Unfortunately, as you scale smaller the SiO2 layer and the overlying Si layer must also shrink and this advantage over bulk gets smaller. I will not go into the disadvantages of SOI (which AMD and IBM will not publicize to the layman press), but they are numerous and are part of what is holding AMD back from ramping clock speeds no doubt.

The metal gate idea you have is indeed backwards... Intel did not put high-K in to play well with metal gate, rather they chose to use metal for the gate electrode because they want to relace SiO2 with a high-K dielectric. What Intel found, and what is published in the literature, is that gate electrodes that are made with metal do not suffer from Fermi Pinning as traditional poly-silicon gate electrodes do. As such, high-K is much more difficult to implement using traditional gate electrodes. The motivation for this technology is because the tried and true SiO2 isolation dielectric used to form the gate has been scaled to the limit. In fact, we hit that limit at 90 nm and it cannot go any thinner. You see this with both Intel's and AMD's 65 nm process, Intel could not clock their 65 nm Cedar mills any higher than their 90 nm prescotts, AMD can't even achieve equivalent clocks with thier 90 nm process.

Staying with SOI does not alleviate AMD's need to figure out how to get around this gate dielectric problem, without it they cannot scale the equivalent oxide thickness of the gate, without it they cannot move away from the gate leakage cliff, and without it they will most likely not exceed even 65 nm clock speeds when moving to 45 nm (this last part is my opinion, I have not seen any data one way or the other).

You may want to take a little time studying the device physics, and purpose for these new technologies before you post... or, if it is of no interest to you, then I suggest you refrain from posting at all ... you are bound to get flack

Jack

[YukonTrooper]

I'll believe it when I see it. Phenom was super late out the door and is by all indication a bust. I don't believe AMD anymore after all the hype that was put into their 65nm chips. The way things are going AMD won't have 45nm out the door until 2009 and by then Intel could have even denser chips.

[Andypro1]

JumpingJack: Informative post; thanks.

[Nedjo]

JumpingJack: Informative post; thanks.

Must concur with this!

Didn't see such a constructive post in News section for a long time!

On this, I guess that AMD invested heavily in SOI tech improving it with DSL, and SiGe and they'll go with it in 45nm era inventing something that'll further extend performance scaling… but 45nm does look like wall for SOI, that has served quite well (who would imagine that dual core K8 would reach beyond 3.2 GHz when single core Winchester was introduced?)

[bedlamite]

Uh thanks JampingJack for making it more clear to me.
Looks like ive missed more physics studies than i thought :P

[JumpingJack]

Uh thanks JampingJack for making it more clear to me.
Looks like ive missed more physics studies than i thought :P

Well, I went back and re-read my last paragraph, it did not read the way I intended it....

What I really meant was it pays off to take some time and interest and learn a few details about how the transistor works, the purpose of some of the materials, and such before walking into a discussion.

If you have any specific questions, ask, if I know the answer I will be much more kind ....