AMD to start 45nm ramp in H1 2008

[savantu]

savantu explained it/posted a link, but it got deleted...

..

Back on topic :

http://www.semiconductor.net/article/CA6464480.html

Bulk or SOI? AMD Considering Its Options

David Lammers, News Editor -- Semiconductor International, 7/31/2007 12:30:00 PM

Advanced Micro Devices (AMD, Sunnyvale, Calif.) is still mulling whether to use silicon on insulator (SOI) or bulk silicon technology for its future high-end and mobile products.

“This is in the exploratory phase, and AMD has not made any statements about when it would make a decision to produce next-generation processors in bulk or SOI,” a spokesman said, adding that AMD technologists are asking questions that “are not answered yet, so we are leaving the question open as they look at the issues.”

During a July 26 meeting, AMD executives described the company’s technology and product roadmaps. Doug Grose, senior vice president of manufacturing and supply chain management, said that AMD is “evaluating the mix” of SOI and bulk technologies for 2009 and beyond.....

As late as mid 2007 AMD was still debating what to do at the 45nm node and some think they will greatly reduce the process gap with Intel in 2008. LMAO

And for SOI challenges :

http://www.semiconductor.net/index.a...A6464480#69173

One of the major differences between the SOI and Bulk technology for the 45nm and beyond is to control the electostics or the short channel effects. For the bulk technology used by Intel the quantum confinement of carriers is controled by a combination of Hallow source/drain implant, and retrograded channel/substrate doping.

On the other hand, for the SOI technology the quantum confinement of carries in inversion layer is carried out by physically reducing the SOI thickness, Tsoi by narrowing the space between the gate oxide and the buried oxide. To mitigate the short channel effects, 45nm SOI may require 50nm~40nm Tsoi, 30nm~20nm Tsoi for 32nm, and 10nm or less Tsoi for 22nm technology. Such a thin Tsoi causes significant carrier mobility degradation and increase in threshold voltage, Vt. Furthermore, for the scaled devices, the strain induced mobility enhancement techniques become less effective.

This is particularly more so for the thin SOI technology simply because in such a thin ~10nm junction and isolation depths, and channel inversion layer thickness it is extremely difficult to implement GeSi S/D junctions and a large lattice mismatch induced by the relaxed Ge-Si substrate in the channel.

Even for the 45nm SOI technology, the manufacturability of the strain induced mobility enhancement techniques used for 90nm and 65nm may not be feasible. In this respect, the SOI technology for the 45nm and beyond has a significant disadvantage over the bulk technology. IBM and AMD are at the crossroad today to determine extenderability as well as manufacturability of the SOI technology for 45nm and beyond.

The conversion from the SOI to the bulk 45nm technology node has enormous technological and manufacturability challenges. This is because IBM and AMD do not have the required learning experiences such as process, design, reliability and device yield gained from the 90nm and 65nm bulk technology development and mannufacturing. Furthermore, two major new materials were introduced in the bulk 45nm technology: the thermal oxide, SiO2 that was used for 40 years is replaced by HfO2, and the polysilicon gate that was used for over 30 years is replaced by the metal gate.

Today Intel is the only company that is manufacturing the bulk 45nm. If that is true, Intel has enormous advantages over its competitors, particularly if IBM and AMD have to adopt the 45nm bulk technology. This is because Intel must have resolved most of the device, process, reliability, and manufacturability issues as a result of introduction of the new materials and processes.

When the new materials and processes like HfO2, metal gate, and their new processes are introduced, new or unknown faiure mechanisms will be also introduced. Therefore, it is crucial to design test structures so as to bring out the unknown failure mechanisms for early detection, and develop effective E-test and reliability test screens. Such experiences gained through the 90nm and 65nm bulk technology development cycles will give an edge to Intel in successful development of the 45nm technology and beyond.