At last, some news of nForce 7 series! upstream - shouldn't upstream be Hyper-transport or at least 16x+16x? It would make sense if they used Hyper-transport to communicate between SPP, MCP and this chip; but having 16x PCI-E split to 2x 16x?
At last, some news of nForce 7 series! upstream - shouldn't upstream be Hyper-transport or at least 16x+16x? It would make sense if they used Hyper-transport to communicate between SPP, MCP and this chip; but having 16x PCI-E split to 2x 16x?
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