AMD Phenom X3 - Triple-Core for people

[MAS]

subj.

Next week AMD is going to introduce first industry triple-core x86 CPU

http://www.hardtecs4u.com/?id=1189807351,51761,ht4u.php

[Warboy]

subj.

Next week AMD is going to introduce first industry triple-core x86 CPU

http://www.hardtecs4u.com/?id=1189807351,51761,ht4u.php

Wasn't the Xbox360 a triple-core x86 IBM CPU?

[MAS]

powerpc isn't classic x86

[Vapor]

Shouldn't this be in Wamps?

[Lightman]

I'm liking this idea. It will give AMD finer model/price binning and I would be happy with 3 cores if priced accordingly.

I'm wondering how disabling of one core will affect max TDP and max frequency on these chips.

[leomax]

If its true,its another proof that k10 yields are not good.

[adamsleath]

bollox; i bet it neva happens (but forget i said that if it does)

er um will that be a "native" quad core with one core disabled ???????

[ColonelCain]

Shouldn't this be in Wamps?

Probably....

Btw, I like your title. That is exactly what I am praying for as well.

[nn_step]

this is just like Intel's Triple core rumor that never became true....
Processor designers prefer base 2 math, thus 1,2,4,8,16,32,64,128,256,512,...,2^n

[madcho]

this is just like Intel's Triple core rumor that never became true....
Processor designers prefer base 2 math, thus 1,2,4,8,16,32,64,128,256,512,...,2^n

i agree, but tripple core with the old opteron is not impossible with a 2P server.

[nn_step]

i agree, but tripple core with the old opteron is not impossible with a 2P server.

please let me know exactly how you get 6 to be 2^n, where n is an integer

[Fairydust]

Zudem habe der Hersteller ebenfalls noch darauf hingewiesen, dass es sich bei den Triple-Kern-Versionen nicht um Vier-Kern-Modelle mit einem deaktiviertem Kern handele, sondern um echte Drei-Kern-Prozessoren.

Additionally the manufacturer pointed out these triple-core Versions are not quad-cores that have 1 core disabled, but genuine triple-cores.

[BrownTown]

There is honestly no reason I can think of why you need 2^n cores, there is nothing about the arrangement that requires a power of 2 cores, obviously in some obscure part of the northbridge you might need have a few bits which were not fully utilized, but that would be essentially nothing. However, there are certainly many good reasons for not having 2^n cores, first off you can rebrand defective chips as triple cores and such which makes a "true quadcore" design more cost effective since the broken ones are worth more than otherwise. Also, once you get past 4 cores it really is usefull, for example going to 8 cores after 4 is a big leap, maybe 6 would be better. And after that 10 instead of all the way to 16. The Xbox360 has 3 cores, the PS3 has 7 SPEs, Intel is prototyping an 80 core CPU, clearly 2^n has little or no good reason. I remember caches doubling, but penryn now has 6MB not 8 like you might have thought, sure that means you have some multiplexers that are optimally fast, and tags that are optimally used, but the inefficiencies are negligible compared to the cost of the extra 2MB (in terms of both size and yields). Using 3 or 6 cores is the same idea, lets you get more cores without killing your pricepoint.

[adamsleath]

uhuh; i say hoax.

let's see the pic of a triple core cpu die

but if they make a cheapy tri core who am i to complain.

let the rumours fly

let's see a quincore (dat's 5)

[iddqd]

If its true,its another proof that k10 yields are not good.

And celeron is proof that c2d yields are not good. Amirite guys?

[metro.cl]

Additionally the manufacturer pointed out these triple-core Versions are not quad-cores that have 1 core disabled, but genuine triple-cores.

Doesnt make sense at all.

[BeardyMan]

what i can make form this is the dismise of single core finally.

Low end dual
mid end tripple
high end quad

[NH|Delph1]

Doesnt make sense at all.

I would have to agree with that ...

//Andreas

[Shintai]

And celeron is proof that c2d yields are not good. Amirite guys?

Celeron is a whole other die with no second core.

But this was expected with the suicidal native quadcore. Its damage control.

[BeardyMan]

Celeron is a whole other die with no second core.

But this was expected with the suicidal native quadcore. Its damage control.

man youre just jalous that your BIG intel couldn't cutt it

Deal with it AMD was the first with a true quad core.

[Motiv]

Doesnt make sense at all.

It does make sense as long as Cache is increased where the 4th core would of been.

If a tri-core had 1mb L2 cache and 4mb L3, it wouldn't be such a bad trade off.

Still, I say it's all bs.

[metro.cl]

man youre just jalous that your BIG intel couldn't cutt it

Deal with it AMD was the first with a true quad core.

That is true and will be for the history but i bet you that if AMD could they wouldnt do it again...


Oh wait they wont Montreal is 2 Quad glued

[metro.cl]

It does make sense as long as Cache is increased where the 4th core would of been.

If a tri-core had 1mb L2 cache and 4mb L3, it wouldn't be such a bad trade off.

Still, I say it's all bs.

It doesnt you have to understand the manuf process, is hard to get the full 4 cores to work at a defined speed that is why you always have a arch that is "cut" from high end to low end.

G80>G86>G84
HD 2900 > HD 2600 > HD 2400


clock speed diferential is also more of an production thing that also is a perfect fit with the demand.

So you make a Quad if not good you have a Triple and if not good you have a dual core.

But trying ot get a Quad only and a Triple only is weird

[savantu]

I am really curios to see whether AMD will make a completely different die layout , makes no sense.
However , I accept 4 core die with one not working ; that's more plausible.

[perkam]

Too wild for my tastes.

CLOSED

Perkam