Quote Originally Posted by JVguest View Post
No, not of course. The L3 adds a L3 eviction and write back penalty on an L3 miss (in addition to L1 and L2), but the improved DRAM prefetchers, buffers and crossbar should be making up for it. It looks to me like 40 cpu clock cycles are being eaten up.
There is a penalty for having L3 cache if the miss goes straight through and requires access to memory, no way around that.... you will spend the extra time snooping the L3 that normally would not have occured if L3 was not there.... so it gets in the way a little.... the net benefit should be positive though so long as the compounded latency is much less than a call to main memory for all the hits.