K10 Scores starting to surface

[adamsleath]

nice figures....but the equating of k10 to real figures is....purely hypothetical.

how is the k8=100% (@1900) and k10=132% (@1900) derived? - does this assume a 32% gain for k10 over k8 baseline?

and does it also assume identical scaling for k10 versus an old p4?

[KTE]

nice figures....but the equating of k10 to real figures is....purely hypothetical.

It can get far worse believe me.

One of the points I wanted to show is how it clearly and perilously casts doubts on this http://img.coolaler.com.tw/images/zm...mlwemyzmzk.jpg compared to this http://img527.imageshack.us/img527/6582/sp47cj7.jpg

Bro, that was 1x 512MB RAM not even dual channel and an old CD. A P4 will get 10 seconds lower at least, beating the Barcelona quad core time they showed.

how is the k8=100% (@1900) and k10=132% (@1900) derived? - does this assume a 32% gain for k10 over k8 baseline?

Yes, the K8 1900 was baseline compared to a K10 1900 - as an assumption for better clock per clock performance. It could be far lower, obviously, but this is a vague explanatory comparison of what Gary stated rather than a "prediction".

What I was saying is, Gary of Anandtech could be basing his statements on similar performance scaling he saw with the K10, as I did with the Celeron chip.

and does it also assume identical scaling for k10 versus an old p4?

Yes. It's not impossible is what I'm saying. Look at how the numbers fluctuate with the Celeron and where. Pure technical math cannot account for this, so we won't be able to explain it, but we'll experience it. It's possible that K10 at lower clocks does not scale as well as some higher clocks. I've just shown you in one application how my old Celeron did it, which means it's entirely possible.

[freeloader]

It can get far worse believe me.

One of the points I wanted to show is how it clearly and perilously casts doubts on this http://img.coolaler.com.tw/images/zm...mlwemyzmzk.jpg compared to this http://img527.imageshack.us/img527/6582/sp47cj7.jpg

Bro, that was 1x 512MB RAM not even dual channel and an old CD. A P4 will get 10 seconds lower at least, beating the Barcelona quad core time they showed.
Yes, the K8 1900 was baseline compared to a K10 1900 - as an assumption for better clock per clock performance. It could be far lower, obviously, but this is a vague explanatory comparison of what Gary stated rather than a "prediction".

What I was saying is, Gary of Anandtech could be basing his statements on similar performance scaling he saw with the K10, as I did with the Celeron chip.
Yes. It's not impossible is what I'm saying. Look at how the numbers fluctuate with the Celeron and where. Pure technical math cannot account for this, so we won't be able to explain it, but we'll experience it. It's possible that K10 at lower clocks does not scale as well as some higher clocks. I've just shown you in one application how my old Celeron did it, which means it's entirely possible.

That's definitely interesting. I guess I'm so used to seeing "linear" scaling, that I didn't give it much thought. It will definitely be cool to see otherwise with K10.

Just a guess here concering SuperPI. Is it possible that we'll see non linear scores due to the L3 cache having decreased latency as the core clock scales higher or is the latency always the same, no matter what the core is clocked at?

[CoW]8(0)]

That's definitely interesting. I guess I'm so used to seeing "linear" scaling, that I didn't give it much thought. It will definitely be cool to see otherwise with K10.

Just a guess here concering SuperPI. Is it possible that we'll see non linear scores due to the L3 cache having decreased latency as the core clock scales higher or is the latency always the same, no matter what the core is clocked at?

You're thinking in the time domain again. The number of clock cycles for code to execute will always be the same regardless of how long those clock cycles are.

So to answer your question, no. It will not affect the scaling.

[freeloader]

You're thinking in the time domain again. The number of clock cycles for code to execute will always be the same regardless of how long those clock cycles are.

So to answer your question, no. It will not affect the scaling.

So basically you're telling me that a 2ghz Barcelona would have the same L3 cache latency (any cache latency for that fact) as a 3ghz Barcelona? Thanks for helping out with this stuff, it's interesting.

[Lightman]

So basically you're telling me that a 2ghz Barcelona would have the same L3 cache latency (any cache latency for that fact) as a 3ghz Barcelona? Thanks for helping out with this stuff, it's interesting.

I would say opposite, but this is only my opinion....
For me it will be like doing SuperPi with DDR2 667 4-4-4 and DDR2 800 4-4-4 on same CPU.
With faster K10 cores you will get differently clocked northbridge which clocks cache L3. It also will be possible to change cache frequency...

Don't take it as a certain, this is just speculation .

[informal]

....people didn't get the chance to notice my post there,i will repost it here :

AMD Phenom X4 can do 3GHz and above

By normal air cool, the AMD Phenom X4 can go beyond the 3GHz mark by overclocking. Although this can be done, there are some stability issues at such high speed.

Currently, there aren't any options to turn off one or two of the cores. Running it in single channel memory helps to stabilise it.

http://my.ocworkbench.com/bbs/showth...200#post420200

Bluetooth is one of those guys who is credible and who got the one of the 1st GA RD790 mobos to test.So this is very good news coming from them!

Note he says air cooling is used and it's a X4 ,so all of the cores must work at the same clock since something is wrong(bios?) and they can't use separate PLLs to clock the cores individually.

[CoW]8(0)]

So basically you're telling me that a 2ghz Barcelona would have the same L3 cache latency (any cache latency for that fact) as a 3ghz Barcelona? Thanks for helping out with this stuff, it's interesting.

No, I'm saying it won't affect the scaling. Why is there a latency decrease when you increase frequency.

As you increase frequency, time decreases (latency). That's why there's a latency decrease and that's why I believe it will scale the same.

[JumpingJack]

No, I'm saying it won't affect the scaling. Why is there a latency decrease when you increase frequency.

As you increase frequency, time decreases (latency). That's why there's a latency decrease and that's why I believe it will scale the same.

Clock cycle latency remains the same..... though you understand the concept I will state it anyway an example:

12 cycles of L2 latency at 2 GHz gives 6 ns latency in time.
12 cycles of L2 latency at 3 GHz gives 4 ns latency in time.

The total time to propogate a signal through the chip has a ceiling, hence as you decrase the clock period at fixed cycle latency -- the wall will be hit and no more clocks for you

It seems a lot of people have a hard time understanding the digitial tick of a clock and the time period for that tick and how that translates into scaling.

[freeloader]

No, I'm saying it won't affect the scaling. Why is there a latency decrease when you increase frequency.

As you increase frequency, time decreases (latency). That's why there's a latency decrease and that's why I believe it will scale the same.

OK, now I fully understand. Thanks!

[JumpingJack]

nice figures....but the equating of k10 to real figures is....purely hypothetical.

how is the k8=100% (@1900) and k10=132% (@1900) derived? - does this assume a 32% gain for k10 over k8 baseline?

and does it also assume identical scaling for k10 versus an old p4?

Don't believe his data, there are two typo's and he misinterpreted it.