K10 Scores starting to surface

[cpuz]

http://img.coolaler.com.tw/images/jj...mckdzozmt1.jpg

15 cycle L2 is vs. 12 cycle Penryn L2 (for 6 TIMES the L2 cache per core)

45 cycle L3.

At least that shows that all cache levels are enabled.
(latency gets the size by measuring the access time, unlike cpuz that relies on the cpuid outputs)

[terrace215]

At least that shows that all cache levels are enabled.
(latency gets the size by measuring the access time, unlike cpuz that relies on the cpuid outputs)

Why do people question those results any longer? The anand guy later confirmed that these results are like the results they are seeing... and that people were likely to be disappointed until AMD can get the clock speeds up.

[savantu]

At least that shows that all cache levels are enabled.
(latency gets the size by measuring the access time, unlike cpuz that relies on the cpuid outputs)

Did you really expect otherwise ?