AMD's 3GHz K10 to break 30,000 3DMark06 (Inq)

[savantu]

I agree that Penryn's memory sub-system is incredible, but lets have a bit more faith in AMD.

One of the greatest strengths of the Athlon/Hammer and now Barcelona, is that it has a large L1 cache.

The K10 improves upon the L1 cache in Hammer by making it two port.

That's very debatable ; large&slow vs small&fast is a never-ending debate.
You need to take into account that the L1 is also only 2 ways , which kinda sucks.

Also, Shanghai (the 45nm successor for Barcelona) still has the same L2 cache size, while the L3 cache is expanded to 6MB.

Because of this, it seems that the AMD engineers didn't think the size of the L2 cache in K10 was going to limit it's performance, otherwise they would have addressed it in Shanghai.

The problem here is die size ; even if they wanted they couldn't put more cache on the 65nm version.At 283mm^2 it looks to be beyond what AMD's FAB can muster , at least for now.Yields are probably very poor , there is a lot of device variation which prevents them for shipping stable higher clocked parts.

On 45nm there are extreme problems awaiting AMD ; you can check for yourself here :

http://www.semiconductor.net/article/CA6464480.html

This reply explains it in great detail :

Submitted by: Sang U. Kim, Ph.D (kimsang@wbhsi.com)
8/1/2007 2:29:13 PM PT
Location: Pheonix, Arizona
Occupation: retired, but active tehcnically

One of the major differences between the SOI and Bulk technology for the 45nm and beyond is to control the electostics or the short channel effects. For the bulk technology used by Intel the quantum confinement of carriers is controled by a combination of Hallow source/drain implant, and retrograded channel/substrate doping. On the other hand, for the SOI technology the quantum confinement of carries in inversion layer is carried out by physically reducing the SOI thickness, Tsoi by narrowing the space between the gate oxide and the buried oxide. To mitigate the short channel effects, 45nm SOI may require 50nm~40nm Tsoi, 30nm~20nm Tsoi for 32nm, and 10nm or less Tsoi for 22nm technology. Such a thin Tsoi causes significant carrier mobility degradation and increase in threshold voltage, Vt. Furthermore, for the scaled devices, the strain induced mobility enhancement techniques become less effective. This is particularly more so for the thin SOI technology simply because in such a thin ~10nm junction and isolation depths, and channel inversion layer thickness it is extremely difficult to implement GeSi S/D junctions and a large lattice mismatch induced by the relaxed Ge-Si substrate in the channel.

Even for the 45nm SOI technology, the manufacturability of the strain induced mobility enhancement techniques used for 90nm and 65nm may not be feasible. In this respect, the SOI technology for the 45nm and beyond has a significant disadvantage over the bulk technology. IBM and AMD are at the crossroad today to determine extenderability as well as manufacturability of the SOI technology for 45nm and beyond. The conversion from the SOI to the bulk 45nm technology node has enormous technological and manufacturability challenges. This is because IBM and AMD do not have the required learning experiences such as process, design, reliability and device yield gained from the 90nm and 65nm bulk technology development and mannufacturing. Furthermore, two major new materials were introduced in the bulk 45nm technology: the thermal oxide, SiO2 that was used for 40 years is replaced by HfO2, and the polysilicon gate that was used for over 30 years is replaced by the metal gate.

Today Intel is the only company that is manufacturing the bulk 45nm. If that is true, Intel has enormous advantages over its competitors, particularly if IBM and AMD have to adopt the 45nm bulk technology. This is because Intel must have resolved most of the device, process, reliability, and manufacturability issues as a result of introduction of the new materials and processes. When the new materials and processes like HfO2, metal gate, and their new processes are introduced, new or unknown faiure mechanisms will be also introduced. Therefore, it is crucial to design test structures so as to bring out the unknown failure mechanisms for early detection, and develop effective E-test and reliability test screens. Such experiences gained through the 90nm and 65nm bulk technology development cycles will give an edge to Intel in successful development of the 45nm technology and beyond.

[mcbalaban]

heh, i just noticed inquirer disabled the e-mail page. i'm sure someone will share his email addy so that we can spam it to death if this turns out to be bull

The e-mail page works normally.

[Shintai]

I thought Tri-fire was 2xGFX, 1xPHYSICS?

No, thats called trippleplay. And physics is still non existant.

[Shintai]

Yep. I'm not going to agree that they used 3 GPUs, because the Phenom rig photographed at GC 07 had 2.

Anyway, ATi developed a way to where the workload is spread across the 3 GPUs, each card generates different parts of the images, then the data is transferred through the PCIe slot or CrossFire connector (can't remember which, but it's one of those) to the master card (the top card, not the master card with the stupid dongle) where the images are put together and sent to your monitor.

There are more pictures and later pictures with 3. And its transfered via the crossfire bridges. Not PCIe.

[Shintai]

Could it crack 30,000 with an instuction set like say, SSE5?

No, 3Dmark06 would need to be recompiled and recoded for it. Also K10 only contains SSE4A thats 4 instructions. More a PR gimmick than really useful. And it seems it lacks SSSE3 (Supplmentals) aswell.

[Gnarr]

I think what everyone forgets to factor in is that with much higher PCIe bandwidth and more CPU power you can utilize the gpu better. If we take kinc's score and add 1000 for SM2 and SM3 (ok.. maybe a little too much), we only need 11100 in CPU score.

SM2: 11581
SM3: 12798
CPU: 11100

= 30032

[generics_user]

There are more pictures and later pictures with 3. And its transfered via the crossfire bridges. Not PCIe.

also got pictures of 2 card 3ghz CF systems

and it's transfered by both PCIe AND bridge, the bridge just replaces the external dongle which simply transfered the images

[Morais]

nice triple post shintai, you know the edit button?

[CraptacularOne]

I think what everyone forgets to factor in is that with much higher PCIe bandwidth and more CPU power you can utilize the gpu better. If we take kinc's score and add 1000 for SM2 and SM3 (ok.. maybe a little too much), we only need 11100 in CPU score.

SM2: 11581
SM3: 12798
CPU: 11100

= 30032

OH, is that all? ...lmao....

As I said before and as was already said by many, I believe that this score was done with 3 (or more) cards in crossfire.

[Hornet331]

or lower resolution.

[TigeriS]

[QUOTE=savantu;2400130]Intel and AMD know; according to Intel the difference is negligible.AMD OTOH claims native is better , doesn't say by how much.
I expect the truth to be in between.
[quote/]

Well just look at the other benchmarks thread, that'll explains it all. Native is better for HPC solutions, which the K8 and K10 are designed for. Desktop users won't see much difference because there aren't many mainstream software that are multi threaded.

Let's look at the current X2s and Conroe.We can call the K8 X2 as the best MCM-like aproach; 2 cores which are connected by an outside link.
C2D uses a shared L2 , the most "native" aproach.

Shared Cache is not the definition for native multi cores. It's a design choice.
Shared Cache is good for single threaded software or when you're running benchmarks. In real world situations where you use multiple software at the same time, or better known as multi tasking you'll find dedicated L2 Caches more efficient.

You can see this in Quake 4 benchmarks. Conroe's performance is hit by a larger margin compared to the X2 when you enable SMP. That's because the shared Cache suffers from "cache conflicts". Dedicated cache will not have that problem. It's just a choice and does not mean it's more native than another.

Time and time again K8 showed it was in no way bottlenecked by its memory sysytem.It only cares about low latency.

Trust me on this, the K8 does not only care about latency, the K8 simply can not handle higher bandwidth, than a given max. Right now DDR2 has gone over that line. Seek it up in AMD's document if you don't trust me.

K10 major flaw is in its cache size ; 512KB is small and the L3 will be a bottleneck.Also its latency if true ( 38 ) is horrible compared with K8/C2D/Penryn ( 12-14 ) .Latest reports put Penryn's massive L2 at 13 cycle latency which is nothing short of astounding.

I don't think it's small, the IMC will take care of that.

Umh , not exactly.The changes made will offer sizable benefits for existing code.

Well just take a look at the other Benchmark thread, you'll see most of my statements confirmed. See in Cinebench you can clearly see that professional software can make a huge difference. A native Quad Core does look to scale better than an MCM solution agreed?

[red]

http://www.hardocp.com/news.html?new...VzaWFzdCwsLDE=

As for what the noted system would score in this popular benchmark, we would have to inform you that the score Theo saw was about 30% to 35% inflated. And while I wish it was going to work out to be true for the gamers and hardware enthusiasts out there, it is just not going to happen. You can take that to the bank. Phenom FX is going to be a great product that will be extremely competitive with current Core 2 architecture, but let's not inflate our expectations artificially.

So he thinks 3GHz K10 would do ~22.5K.

[FlawleZ]

http://www.hardocp.com/news.html?new...VzaWFzdCwsLDE=


So he thinks 3GHz K10 would do ~22.5K.

Very interesting. But even at 30% that's no more than 21K. At 35%, we're looking at ~18.5K. Let's hope he's over predicting here.

[Hornet331]

I don't think it's small, the IMC will take care of that.

hu..? the ram has even more latency than the 3rd level cache...

[JVguest]

[QUOTE=TigeriS;2402324]

Intel and AMD know; according to Intel the difference is negligible.AMD OTOH claims native is better , doesn't say by how much.
I expect the truth to be in between.
[quote/]

Well just look at the other benchmarks thread, that'll explains it all. Native is better for HPC solutions, which the K8 and K10 are designed for. Desktop users won't see much difference because there aren't many mainstream software that are multi threaded.



Shared Cache is not the definition for native multi cores. It's a design choice.
Shared Cache is good for single threaded software or when you're running benchmarks. In real world situations where you use multiple software at the same time, or better known as multi tasking you'll find dedicated L2 Caches more efficient.

You can see this in Quake 4 benchmarks. Conroe's performance is hit by a larger margin compared to the X2 when you enable SMP. That's because the shared Cache suffers from "cache conflicts". Dedicated cache will not have that problem. It's just a choice and does not mean it's more native than another.



Trust me on this, the K8 does not only care about latency, the K8 simply can not handle higher bandwidth, than a given max. Right now DDR2 has gone over that line. Seek it up in AMD's document if you don't trust me.



I don't think it's small, the IMC will take care of that.



Well just take a look at the other Benchmark thread, you'll see most of my statements confirmed. See in Cinebench you can clearly see that professional software can make a huge difference. A native Quad Core does look to scale better than an MCM solution agreed?

K8/K10 scaling is and will be better than Core 2/Penryn because there is no FSB and cache coherency traffic is handled by HT links. However raw performance is outstanding for Core 2 so the scaling degradation doesn't matter so much. Yes, when both cores access shared L2 the bandwidth to both cores drops, but the large L2 ensures a good hit rate from the L2 cache, meaning slow RAM accesses are limited. Running dual superpi or F@H SMP core 2 is much faster than K8, and SMP F@H datasets run near 768 MB at max. Fast RAM is also pretty much useless on Core 2 unless you overclock the FSB. Then it really starts to fly.

Looking forward to seeing K10 in action with it's 32 byte fetch and improved BPU/OOO and floating point units even if it does clock at only 2-2.3 GHz. Intel hasn't exactly been quickly ramping clockspeeds on Core 2 duo recently.

[Zytek_Fan]

If anybody saw the thing on [H]ardOCP on the thread they have for this, don't pay attention. I'm becoming more and more suspicious that Kyle and all of [H] is being payed off by Intel and NVIDIA.

[informal]

If anybody saw the thing on [H]ardOCP on the thread they have for this, don't pay attention. I'm becoming more and more suspicious that Kyle and all of [H] is being payed off by Intel and NVIDIA.

Common you are joking ,right ?

[Start]

If anybody saw the thing on [H]ardOCP on the thread they have for this, don't pay attention. I'm becoming more and more suspicious that Kyle and all of [H] is being payed off by Intel and NVIDIA.

The Nvidia side I can see that being true. The Intel, not sure about that one.

[Zytek_Fan]

Common you are joking ,right ?

There has been a lot of talk in our forums about the Inq posting a story noting 30K+ 3DMark 06 scores with a Phenom FX / Agena core AMD next-gen processor. Let me just call a spade a spade here and tell you that this story is wrong. A 3GHz “K10” and 2900 XT CF system as noted below is NOT going to give you a 30K score in 3DMark06.

The particular processor was none other than a single socket Barcelona or Agena FX, call it what you will. The reference motherboard containing RD790 chipset packed two HD 2900XT cards, and the memory installed was Corsair’s Dominator PC2-9136C5D, or the same ones we have been using ever since they came out. There was a Raptor hard drive, and that was about that. OCZ will like the fact that PP&C Quaddie CrossFire PSU was installed in the system.

When clocked at 3.0 GHz and equipped with two overclocked HD2900XT cards in CrossFire, Agena FX or single-core Barcelona smashed an index of 30,000 3DMarks 06.

I know Theo Valich, the author of this story quoted above. While he might have very well seen what is being reported, it is not going to be reproducible in a controlled test environment. I have to think that someone was pulling the wool over his eyes. As for motivations, who knows?

As for what the noted system would score in this popular benchmark, we would have to inform you that the score Theo saw was about 30% to 35% inflated. And while I wish it was going to work out to be true for the gamers and hardware enthusiasts out there, it is just not going to happen. You can take that to the bank. Phenom FX is going to be a great product that will be extremely competitive with current Core 2 architecture, but let's not inflate our expectations artificially.

How can he say something like that with no official confirmation that it is true or false. Rather than claim it's all false, he could have taken the neutral standpoint and explained it could be true because... and it could be false because...

[Zytek_Fan]

The Nvidia side I can see that being true. The Intel, not sure about that one.

The Nvidia one is obvious with all the reviews that include the Radeon HD2900XT it says Nvidia has all the better settings and such. Did he even try to run the same settings with the 2900XT? No.

When I look for reviews I go to Guru3D, Bit-Tech, and VR-Zone

[nr2134]

The Nvidia side I can see that being true. The Intel, not sure about that one.

Ill second that. A certain C2D review comes to mind when Kyle said to wait for the new AMD CPU before making a leap to Intel C2D. Thats after the C2D walked all over AMD offerings @ that time.

[Zytek_Fan]

Ill second that. A certain C2D review comes to mind when Kyle said to wait for the new AMD CPU before making a leap to Intel C2D. Thats after the C2D walked all over AMD offerings @ that time.

That's because it's bad from a consumer standpoint to leap out and get the first thing that strikes your fancy.

[Zytek_Fan]

Oh, come on..
If anything I would think that [H] is being payed by AMD. Just look at their X2 vs C2 comparisons. They used higher quality settings on the C2 system and came to conclusion that both systems perform same.

That guy Kyle(whoever he is) was only using common sense. 3D Mark if anything is GPU bounded and only miracle(from the AMD fanpois dreams) can make it a CPU bounded synthetic benchmark. Also, a rumor comming from the_INQ article should be taken with a graint of salt, considering their rumor hit rate(less than 50%). The article is only clueless BS and Theo is a known noob without a basic knowledge about the rumors he uses to spread (for example ReverseHyperThreading).

Like I said he could of at least stated both sides of the argument as opposed to the one claiming all is false.

[mcbalaban]

...I'll bet in all my savings(around 24K Euros) that a K10 at 3GHz & 2x2900XT can't score 30K in 3DM2K6.

Ooooooo.... That's a lot of savings....!

What's your secret?

[Face]

If anybody saw the thing on [H]ardOCP on the thread they have for this, don't pay attention. I'm becoming more and more suspicious that Kyle and all of [H] is being payed off by Intel and NVIDIA.

How can he say something like that with no official confirmation that it is true or false. Rather than claim it's all false, he could have taken the neutral standpoint and explained it could be true because... and it could be false because...

I think your'e wrong, and I must disagree with you this time.

Kyle Bennet is under NDA and he has already seen several Barcelona benchamarks(search for the Barcelona demo in San Francisco).

He actually said a few times that Barcelona\Phenom is going to end up faster than Core 2 and that he can't say much more than that.
So it would make much more sense to take his word for it over the highly unlikely Inq report, because there are some things he knows, which gives him a much better idea\estimate of Phenom's strength.

It's also strange, because people have always accused him of being an AMD fan, not the other way around.

But in any case, we should know soon.