why not? the difference between a E6400 and E6600 in the same overclock, same board, and same ram, even in 1M is pretty drastic.
another 2 megs to the cache, would be no different.
4 megs to 6 megs would be a nice jump for PI.
why not? the difference between a E6400 and E6600 in the same overclock, same board, and same ram, even in 1M is pretty drastic.
another 2 megs to the cache, would be no different.
4 megs to 6 megs would be a nice jump for PI.
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thanks for the numbersit looks like a winner with 6MBs of L2
True but everest is on par with C2D, i just dont want to make false hopes, if it does that time greatOriginally Posted by Kunaak
SSE4 is fairly new. Is it not possible that his beta copy of Everest is not optimize to run SSE4?True but everest is on par with C2D, i just dont want to make false hopes, if it does that time great
Last edited by Eastcoasthandle; 06-22-2007 at 01:54 AM.
[SIGPIC][/SIGPIC]
Look at the second Everest benchmark.
Yeah, I see that but it's still a beta, that's why I asked.
[SIGPIC][/SIGPIC]
I agree. Assuming the extra cache allows full performance scaling and isnt bottlenecked by something else, and SSE4 does its thing, it should take towards 2 secs off a Spi 1M time compared to a 4MB Conroe at the same clocks.
Penryn @ 3600MHz should be around....12-12.2 secs?
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