DDR3 high speeds and high latencies

[Tony]

All AM2 needs is 1 module around 1000 4-4-4 1T and you have all the bandwidth and low latency the CPU needs, its also a lot easier to tweak 1 module due to less load.

C2D is just the same really, shorter pipes and a need for fast access latency, so you may find running 1 DDR3 module is the fastest option as long as the speed is huge and the overall latency real low.

All we need is 1T implemented on DDR3 and we should be good to go with 1 module benching IMO

[EnJoY]

Tony, have you done any tests comparing single channel to dual channel? Is the extra overclockability/timing tightening ability with a single dimm enough to overshadow the greater bandwidth of dual channel?

[_damien_]

Yeah, if the memory controller cannot take advantage of the high bandwidth, it becomes a total waste and the high latency becomes a problem.
Think about socket 939 and AM2, we all know 939 is faster than AM2 in many ways, becuase the memory controller of AM2 cannot make full use of the DDR2 bandwidth.

Actually, I don't know that. Just because the CPU doesn't *need* it, doesn't make the excess bandwidth a drawback. On the contrary - high BW adds flexibility. One can drastically reduce the memory speed and aim at tighter timings instead, without compromising performance. That's especially relevant for AM2 systems, where there are huge clock gaps between the dividers. Furthermore, high bandwidth improves loaded latency as well, which is the only relevant type of latency.

All AM2 needs is 1 module around 1000 4-4-4 1T and you have all the bandwidth and low latency the CPU needs, its also a lot easier to tweak 1 module due to less load.

C2D is just the same really, shorter pipes and a need for fast access latency, so you may find running 1 DDR3 module is the fastest option as long as the speed is huge and the overall latency real low.

All we need is 1T implemented on DDR3 and we should be good to go with 1 module benching IMO

While I do agree that the performance would be perfectly adequate, every tiny gain makes a difference when benching, and having multiple banks will always be an advantage because it allows for latency hiding. So it would surprise me a lot if running one stick would prove to be the fastest option.

In fact, a page hit allows the memory to even skip certain operations, and the more banks, the fewer rows would be allocated per bank. Et cetera... (I assume you are well aware of this, even though the view expressed here suggests otherwise).

When K10 introduces channel interleaving later this year, there'll be another advantage to using multiple modules. The independent controllers will be able to perform concurrent reads and writes, in addition to yielding improved command efficiency. And channel interleaving will obviously require at least two modules.

BTW I seriously doubt that a CPU's memory preference would be dictated by its pipeline-depth.