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Thread: [XF] GeIL DDR3-1066 CL6

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  1. #1
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    Quote Originally Posted by NinjaZX6R View Post

    You have to admit though, PC8500 at 6-6-6 isn't exactly ground breaking
    For early DDR3 it's pretty good. Standard DDR3 with 6-6-6 timings runs at 400MHz (PC3-6400).
    Don't confuse this with DDR2. You should compare it like this:

    PC2-6400 (400MHz) with a CAS of 5 (like early DDR2)
    1 clockcycle equals 1/400,000,000th of a second or 2.5ns (nanoseconds)
    A total latency of 5 × 2.5 = 12.5ns

    PC3-8500 (533MHz) with a CAS of 6
    1 clockcycle equals 1/533,000,000th of a second or 1.875ns
    A total latency of 6 × 1.875 = 11.25ns

    As you can see the DDR3 module has a lower latency. But that's not even the most important benefit. The real benefit lies in the bandwidth.
    DDR3 will scale all the way up to PC3-12800 (12.8GB/s) and even further. The highest DDR2 ever managed was 11.7GB/s and that's DDR2 at 732MHz (PC2-11712).
    Last edited by Rone; 04-24-2007 at 03:46 PM.

  2. #2
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    Quote Originally Posted by r00n View Post
    For early DDR3 it's pretty good. Standard DDR3 with 6-6-6 timings runs at 400MHz (PC3-6400).
    Don't confuse this with DDR2. You should compare it like this:

    PC2-6400 (400MHz) with a CAS of 5 (like early DDR2)
    1 clockcyle equals 1/400,000,000th of a second or 2.5ns (nanoseconds)
    A total latency of 5 × 2.5 = 12.5ns

    PC3-8500 (533MHz) with a CAS of 6
    1 clockcycle equals 1/533,000,000th of a second or 1.875ns
    A total latency of 6 × 1.875 = 11.25ns

    As you can see the DDR3 module has a lower latency. But that's not even the most important benefit. The real benefit lies in the bandwidth.
    DDR3 will scale all the way up to PC3-12800 (12.8GB/s) and even further. The highest DDR2 ever managed was 11.7GB/s and that's DDR2 at 732MHz (PC2-11712).
    Thanks r00n, that actually clears up a lot. I really appreciate your time/insight. I guess that in time, DDR3 will REALLY start to show its benefits.

    -Collin-
    I am like an alcoholic, but with motherboards.

  3. #3
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    Quote Originally Posted by r00n View Post
    For early DDR3 it's pretty good. Standard DDR3 with 6-6-6 timings runs at 400MHz (PC3-6400).
    Don't confuse this with DDR2. You should compare it like this:

    PC2-6400 (400MHz) with a CAS of 5 (like early DDR2)
    1 clockcycle equals 1/400,000,000th of a second or 2.5ns (nanoseconds)
    A total latency of 5 × 2.5 = 12.5ns

    PC3-8500 (533MHz) with a CAS of 6
    1 clockcycle equals 1/533,000,000th of a second or 1.875ns
    A total latency of 6 × 1.875 = 11.25ns

    As you can see the DDR3 module has a lower latency. But that's not even the most important benefit. The real benefit lies in the bandwidth.
    DDR3 will scale all the way up to PC3-12800 (12.8GB/s) and even further. The highest DDR2 ever managed was 11.7GB/s and that's DDR2 at 732MHz (PC2-11712).
    I did NOT know that! I'm sure a few others don't either. thanks for the quick explanation yo

  4. #4
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    Quote Originally Posted by r00n View Post
    For early DDR3 it's pretty good. Standard DDR3 with 6-6-6 timings runs at 400MHz (PC3-6400).
    Don't confuse this with DDR2. You should compare it like this:

    PC2-6400 (400MHz) with a CAS of 5 (like early DDR2)
    1 clockcycle equals 1/400,000,000th of a second or 2.5ns (nanoseconds)
    A total latency of 5 × 2.5 = 12.5ns

    PC3-8500 (533MHz) with a CAS of 6
    1 clockcycle equals 1/533,000,000th of a second or 1.875ns
    A total latency of 6 × 1.875 = 11.25ns

    As you can see the DDR3 module has a lower latency. But that's not even the most important benefit. The real benefit lies in the bandwidth.
    DDR3 will scale all the way up to PC3-12800 (12.8GB/s) and even further. The highest DDR2 ever managed was 11.7GB/s and that's DDR2 at 732MHz (PC2-11712).
    maybe 13354mb/s was the highest
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  5. #5
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    Quote Originally Posted by msimax View Post
    The above was done with four modules. The advantages of Dual Channel and Bank Interleave are clearly visible.
    I was talking about a single DDR2 and DDR3 memory module, without Dual Channel and Bank Interleave.
    Last edited by Rone; 04-25-2007 at 03:28 AM.

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