Yorkfield question?

[XS Janus]

Do you guys know if the upcoming Intel CPU will work on current 965 boards + JUST a new bios, OR will there be the need for new board revision with some hardware changes on it to be compatible with Yorkfield??

I know there is going to be a whole new chipset for it but it would be good if one could "pace" their upgrade somewhat.
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Recall Paxil

[XS Janus]

Nobody knows anything yet??
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Avandia Death

[Hajpoj]

Yorkfield is going to be 800FSB right? The only possible problem could be it's voltage requirement. But any decent core2 mobo has a very broad voltage scale, so it should work fine.

Meaning a bios upgrade at most, for the cpu's proper voltage to be detected etc.

[sierra_bound]

Yorkfield will have a 1333MHz FSB. It will be go in boards with the upcoming Bearlake chipset which will be the replacement for 965 and 975X.

There will be at least four different Bearlake versions. Bearlake-X will have support for dual graphics cards and PCI Express 2.0.

[XS Janus]

Yorkfield will have a 1333MHz FSB. It will be go in boards with the upcoming Bearlake chipset which will be the replacement for 965 and 975X.

There will be at least four different Bearlake versions. Bearlake-X will have support for dual graphics cards and PCI Express 2.0.

I know the new "Bearlake" boards will be THE ones to have.
But in some roadmaps I've seen that Yorkfield will be 1066/1333 models and since todays boards can allready work with 1333 that lead me to this question.
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Lovely Wendie

[[XC] Teroedni]

Thread revival

I just wonder what the difference between Kentsfield and Yorkfield will be?
I know it be 45 nm and probably clock greats
And that it will come with a 1333 fsb, and will be released in Q3 this year.

But what other difference is there?
Will it be native quad core?


Thanks

[sierra_bound]

Yorkfield will feature the new Penryn instruction set. It will have 12MB of L2 cache.

Aside from that, we don't know much else. Yorkfield is meant for the upcoming Bearlake platform which will feature PCI Express 2.0 and a new southbridge (ICH9).

[TuKo]

Yorkfield ES are already getting around, with new chipset, 1333MHz FSB and DDR3 samples.

[sierra_bound]

Yorkfield ES are already getting around, with new chipset, 1333MHz FSB and DDR3 samples.

It is? Where? Maybe Intel engineers and manufacturers have it. But I haven't seen it out in the wild.

[Turtle 1]

Thread revival

I just wonder what the difference between Kentsfield and Yorkfield will be?
I know it be 45 nm and probably clock greats
And that it will come with a 1333 fsb, and will be released in Q3 this year.

But what other difference is there?
Will it be native quad core?


Thanks

Here's whats been around at differant sites.

1) 45nm with high k and metal gates.

2) DDR3


3) 12mb of shared cache all 4 cores.

4) 30 new sse4 instructions

Since its a modular design Intel may have beefed it up more its unknown . But Since Intel canceled spring IDF 07 Intel may very well be beefing it up. Or there is nothing new to report so they canceled IDF.

[XS Janus]

Cool!
Thanks Turtle1, keep on snooping
________
Medical Marijuana

[[XC] Teroedni]

Turtle 1
Now that you actually promised to stop posting Intel Yorkfield info in the K8l thread , you may perhaps post it here instead

Some question
1.You say DDR3 but will Yorkfield work in older ddr2 Core 2 dou/quad motherboards?


2.And about that 12mb cache. Wikipedia says this

Earlier media reports suggested Yorkfield to be an octa-core (eight-core) processor consisting of 2 dies with four cores each. However the newest rumours indicate that Yorkfield will be the quad-core successor to the Kentsfield processor[16]. It will have a 45 nanometer process, and be a single die design, unlike the Kentsfield, which has been compared to basically two separate Conroe cores in one socket. The Yorkfield will have 8 MiB of fully shared L2 cache (the Kentsfield has two separate 4 MiB L2 caches, shared separately by each pair of processors). An across-the-board increase in bus speed (connection to the northbridge, etc.) to be greater than 1333 MT/s is hoped for by this point, as all processors will be primarily limited by the bus bandwidth. This may prove to be difficult, as past advancements in bus speed have come coupled with changes in how the data is sent. Yorkfield is also expected to be released supporting DDR3 memory (1333 MHz DDR), as suggested by certain enthusiast websites.

so can you link to where you got that 12MIB Shared l2?


3.SSE4 I guess you only see improvements with new programs that use sse4.

4.Any other news regarding Yorkfield please share

[Turtle 1]

Well now that Intel has spoken and shown working Penryns . 12mb of shared is not likely. So it will be 2x6mb. Unless intel added a cross bar between the caches thats very unlikely.

But we do now know it is . HighK and metal gates.

Intel guidence says it will be 20%better performance using the same amount of drive current as the conroe at the same clock. Or you can lower the drive current and it will be more energy efficient. Since this is new tech and a brain new transitor it seems to behavy differantly than past transitors.

Intel also added 17% more transitors to the core logic. Improveing Gameing /Multimedi./Scientic computing . Also these new sse4 instructions its seems adds to the ability of intels refreshed compiler to read high level language and effect better thread parallelism .

It is said these new processor will be very O/C-able . As wellas very energy efficient.

Intel hasn't given out alot of info they seem to be holding back some.
It is rumored that these will be H/T but I find that hard to believe unless intel decided to add all 50 sse4 instructions. Penryn was suppose to recieve only 30 new SSE4 instructions. If penryn got all 50 instructions that means penryn also got a new compiler. It would than also have the ability to read high level language for better parrallelism. Which really doesn't mean much to us unless it has something to do with mitosis.

But the ability to read high level language with better parrallelism would be a big deal on servers. (look up Elbrus a company intel bought in 2004)

[XS Janus]

Oh, God, thanks Turtle1!
This all sounds great, can't wait
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Cala

[Turtle 1]

The bulk of SSE4's 50 or so instructions is comprised of new compiler vectorization primitives, which should make it easier for compilers to translate software written in high-level languages into effectively parallelized code and data structures. These new instructions encompass both integer and floating-point operations, and include provisions for dual- and quad-word multiplication, blending, and format conversions. SSE4 also has some related "media accelerator" functions that expand SSE's capabilities. Among them are four instructions that round floating-point values to integers and a floating-point dot product capability that should prove especially useful for graphics. Taken together, Intel expects these new instructions to help further the traditional promise of SSE as an accelerator for multimedia, 3D gaming, graphics, and scientific computing.

[Turtle 1]

Turtle 1
Now that you actually promised to stop posting Intel Yorkfield info in the K8l thread , you may perhaps post it here instead

Some question
1.You say DDR3 but will Yorkfield work in older ddr2 Core 2 dou/quad motherboards?


2.And about that 12mb cache. Wikipedia says this



so can you link to where you got that 12MIB Shared l2?


3.SSE4 I guess you only see improvements with new programs that use sse4.

4.Any other news regarding Yorkfield please share

your 1) I could post links but I think we all know it will be 2x6mb.

Your 2 already ans. above-Wikipedia- is a good and bad source it depends.

Your 3 is unknown. Some instructions could be improvements of old instructions. Since the white paper has been out for a long time and intel has been actively working with programm writers it unknown. Some of those sse4 instructions work with the compiler which is manages the register

[[XC] Teroedni]

Turtle 1
Please show a link for 2x6mb if you know of any

And i ask again
Will yorkfield work in current Core 2 dou motherboards or will it require new ones?

[Turtle 1]

The 2x6 mb cache are all over the web, you just google yorkfield.

I don't know the ans to your second question other than Intel said the five cpu's they demoed ran on un modded M/B . This question to me doesn't matter. These cpu's will run on a 1333 fsb its also been reported 1066 fsb. Anand tech article lays it out.

To me it just not an interest. As the only chipset I am interested in for this cpu is the X-38 Bearlake.

[Turtle 1]

Well now that Intel has spoken and shown working Penryns . 12mb of shared is not likely. So it will be 2x6mb. Unless intel added a cross bar between the caches thats very unlikely.

But we do now know it is . HighK and metal gates.

Intel guidence says it will be 20%better performance using the same amount of drive current as the conroe at the same clock. Or you can lower the drive current and it will be more energy efficient. Since this is new tech and a brain new transitor it seems to behavy differantly than past transitors.

Intel also added 17% more transitors to the core logic. Improveing Gameing /Multimedi./Scientic computing . Also these new sse4 instructions its seems adds to the ability of intels refreshed compiler to read high level language and effect better thread parallelism .

It is said these new processor will be very O/C-able . As wellas very energy efficient.

Intel hasn't given out alot of info they seem to be holding back some.
It is rumored that these will be H/T but I find that hard to believe unless intel decided to add all 50 sse4 instructions. Penryn was suppose to recieve only 30 new SSE4 instructions. If penryn got all 50 instructions that means penryn also got a new compiler. It would than also have the ability to read high level language for better parrallelism. Which really doesn't mean much to us unless it has something to do with mitosis.

But the ability to read high level language with better parrallelism would be a big deal on servers. (look up Elbrus a company intel bought in 2004)

Its as I thought NO h/T on penryn . Only 30 sse4 instructions will be added. The other 20+ sse4 instructions are reserved for Nehalem which will recieve the new compiler based off of the Elbrus compiler.
I didn't think intel would bring H/T out yet. They just don't need it. As penryn should keep the performance lead.

[Anusha]

I heard Gigabyte DS3 and higher models will support them and FSB1333 with a BIOS upgrade. Also, I think the highend models from Asus will support them too (I mean the P965 based models)

[Turtle 1]

Meh... Bearlake doesn't really have me too excited. It's not a bad platform, I just don't see it offering much over 965/975 boards. DDR3 and PCIe2 is about all it has and those really don't offer much IMHO. If, and this is a big if, Penryn works on 965/975 and you are running one of those platforms I would reccomend doing a CPU upgrade to Penryn, then going to the next platform after that. You won't be sorry.

So are you saying that you don't believe that bearlake X-38 won't attain A higher fsb than current 965 chipsets. Right now its possiable to get DDR3 @ 1333. By the time X38 is released there will be DDR 3 1666 or 1600 which ever. I would think Intel would be looking that far ahead with a High performance chipset. So I am thinking intel will have FSB of 400. quad pumped =1600. Running at DDR800 at 1:1. Thats just my thinking, of course 1333 will be the standard . But this chipset should have the option for DDR3 1600.

[informal]

Its as I thought NO h/T on penryn . Only 30 sse4 instructions will be added. The other 20+ sse4 instructions are reserved for Nehalem which will recieve the new compiler based off of the Elbrus compiler.
I didn't think intel would bring H/T out yet. They just don't need it. As penryn should keep the performance lead.

Lol,you were claiming that there probably WILL be HT on Penryns,not the other way around.You just changed the tune the minute the news broke in.
And how do you know that Penryn will keep the performance lead??Did you see them tested side by side?A haven't seen any benches.
And btw K8 is still competitive in 4-way as for performance.The power usage is higher,but they are moving the K8 to 65nm so the perf/watt will be much better.

[Turtle 1]

Lol,you were claiming that there probably WILL be HT on Penryns,not the other way around.You just changed the tune the minute the news broke in.
And how do you know that Penryn will keep the performance lead??Did you see them tested side by side?A haven't seen any benches.
And btw K8 is still competitive in 4-way as for performance.The power usage is higher,but they are moving the K8 to 65nm so the perf/watt will be much better.

Look at post 21 I clearly never believed it. I have always stated and its in a lots of post the penryn would use only get 30sse4 instructions. The white paper in the Vector processing on nehalem(news section Thread) clearly shows penryn only getting 30 SSE4 instructions.
I only talked about HT on penryn was reported to have H/T which would requirer a new compiler to run all 50 new SSE4 instructions.

I to was in denial about the H/T being on penryn - But I thought well maybe AMDs K8l is a lot better than I thought and intel pulled some things ahead. I have always thought the penryn with HighK and metal gates would be enough to keep the performance lead based off nothing more than a shrink and the new transistors. Solely based of the increase clocks.. Intel is alking a 20 % clock increase for Penryn using the same power envelop.

That would 3.6 for the high end 2 core and as things stand right now but thats based off of a 3.0ghz I think before penryn arrives well see a 3.2+

So the 3.6 - 4.0 ghz penryn as being inline with what we heard . Do I believe a penryn will be faster at 3.6 than AMD @ 2.9 . In the mojotity of apps. yes I do. What does remain to be seen is how well these O/C if they are equal to conroe in over clocking ability. We are looking at 5.ghz O/C as common. For penryn. For myself a 4.75ghz on water is good enough. But other guys here will cranking these things up . Going to be alot of happy guys here. If penryn=conroein O/C-ability

[Turtle 1]

If I were Intel I would have done things differantly. I would have left the L2cache at 4mbs. Used the saved transitors to double the L1 cache size. maybe that would have lowered the clock speeds I don't know. But increaseing L1 it seems to me would be a greater performance leap.

[informal]

Turtle 1,you are talking about OCing the server CPUs man...Tell me what company in the likes of Sun will buy Yorkfields at slower speed bin and OC them?
Quadcore chips will work at their specd speeds,not the way you dream they will.
There will be some small number of enthusiast who will buy them to insert them in in appropriate mobos that allow OCing,but the server market doesn't work that way...
You need to exit that small world of yours where Yorkfield on air will clock to 5GHz.We don't know that.And if they will,power consumption will skyrocket due to higher voltage input and frequency...
And as for which will be faster,Barcelona or Penryn,let's wait for the benchmarks,shall we?Instead of talking bs about 4Ghz+ Penryns and HT that doesn't exist and vector units on Nehalem(which is a late 2008 product).