K8l to have 6mb cache

[agenda2005]

This thread is about the amont of cache on K8L.

AMD's own words on this is 4x512kB L2 and 2MB L3 cache that is expandable, Maybe 3MB, 4MB .....

This is primarily because AMD knows quite well that cache increase gains very little for K8 architecture. Sempron with 256kb L2 are doing well against FX with just as little as 100- 150MHz clock differential.

The anandtech article linked by brentpresley explain most of the needed improvements for K8--> K8L to be more competitive.

It's quite amusing to see people counting their eggs about what K8L will do. Some said 25% higher IPC, some even say 40 + 40 + 20 which is rather silly.

The truth is that AMD will continue to perfom simulation about the expected performance of K8L on paper design, but usually, the tape out product will give a completely diffent result. Therefore any IPC improvement over K8 now is pure speculation at best.

While I would prefer to restrain myself from mentioning anything about Core 2, but I felt it would be rather boring not to do so.

Core 2 architecture for now we know and can buy the product on the open market. Intel actually restrained themselves from predicting what IPC improvement we would get until the product was finished and tested.

All these K8L IPC speculations are pure marketing propanganda and BS to keep AMD customers, especially the server ones happy and hopefull.

The truth is that, K8L or whatever it will be called is still going to be 3 issue Core with a lot of core improvement. This will not change things drastically against Core 2 archtecture that have potential clock headroom aside from boosting a strong OoO execution units, aggresive prefetching and huge cache estate.

Thanks to brentpresley for pointing out the FSB issue with kentsfield. Yes,It's true that Core 2 architecture max out at about 3.4-3.5GHz on the FSB. That's alot of headroom for Intel before DDR3. Core 2 prefecthers are very aggressive and therefore have little use for an on-die memory controller. An on-die MC on Core 2 will be an added bonus, but not anything to be eager about.

There are still quite a lot of tweaking that Intel is doing on the Core 2 architecture and that should make AMD be aware that they have a long way to go.

EDIT: For spelling

[metro.cl]

This thread is about the amont of cache on K8L.

AMD's own words on this is 4x512MB L2 and 2MB L3 cache that is expandable, Maybe 3MB, 4MB .....

This is primarily because AMD knows quite well that cache increase gains very little for K8 architecture. Sempron with 256kb L2 are doing well against FX with just as little as 100- 150MHz clock differential.

The anandtech article linked by brentpresley explain most of the needed improvements for K8--> K8L to be more competitive.

It's quite amusing to see people counting their eggs about what K8L will do. Some said 25% higher IPC, some even say 40 + 40 + 20 which is rather silly.

The truth is that AMD will continue to perfom simulation about the expected performance of K8L on paper design, but usually, the tape out product will give a completely diffent result. Therefore any IPC improvement over K8 now is pure speculation at best.

While I would prefer to restrain myself from mentioning anything about Core 2, but I felt it would be rather boring not to do so.

Core 2 architecture for now we know and can buy the product on the open market. Intel actually restrained themselves from predicting what IPC improvement we would get until the product was finished and tested.

All these K8L IPC speculations are pure marketing propanganda and BS to keep AMD customers, especially the server ones happy and hopefull.

The truth is that, K8L or whatever it will be called is still going to be 3 issue Core with a lot of core improvement. This will not change things drastically against Core 2 archtecture that have potential clock headroom aside from boosting a strong OoO execution units, aggresive prefetching and huge cache estate.

Thanks to brentpresley for pointing out the FSB issue with kentsfield. Yes,It's true that Core 2 architecture max out at about 3.4-3.5GHz on the FSB. That's alot of headroom for Intel before DDR3. Core 2 prefecthers are very aggressive and therefore have little use for an on-die memory controller. An on-die MC on Core 2 will be an added bonus, but not anything to be eager about.

There are still quite a lot of tweaking that Intel is doing on the Core 2 architecture and that should make AMD be aware that they have a long way to go.

EDIT: For spelling

that is like 130392920% improovement

[agenda2005]

that is like 130392920% improovement

You can speculate whatever you like, but making up for 20% lag is quite a lot in the CPU world.

Time will tell, but your 25% IPC improvement of K8L over Conroe is too ambitious IMHO. That is approximately 45% improvement per clock over K8. AMD will have to come out with a perfect design that will fill up the CPU pipeline and extensively utilize the 3 wide issue.

Even Core 2 with its OoO and aggresive prefetchers is only able to sustain one issue per clock cycle. Aside from that Core 2 also have potentially higher clock to execute instructions.

Go and read up man. AMD have their work cut out for them.

[metro.cl]

You can speculate whatever you like, but making up for 20% lag is quite a lot in the CPU world.

Time will tell, but your 25% IPC improvement of K8L over Conroe is too ambitious IMHO. That is approximately 45% improvement per clock over K8. AMD will have to come out with a perfect design that will fill up the CPU pipeline and extensively utilize the 3 wide issue.

Even Core 2 with its OoO and aggresive prefetchers is only able to sustain one issue per clock cycle. Aside from that Core 2 also have potentially higher clock to execute instructions.

Go and read up man. AMD have their work cut out for them.

Also i was kidding couse you put 4x512MB no 4x512kb as it should be

do you know how much ipc improoved from p4 to c2d?

why cant amd improove 25%? time will tell im not making up i got this info from the same person that told me 9 months before that:

C2D would kill amd
C2D would have cold bug
C2D would get over 3.6GHz OC

so i trust him

[metro.cl]

C2D cold bug? You left a NOT out of there right?

they do with ln2

[Turtle 1]

they do with ln2

Breaks bring browser to screaming hault. User screams LINK PLEASE!!!!!

[Cooper]

Breaks bring browser to screaming hault. User screams LINK PLEASE!!!!!

Just ask few guys here who use LN2

[nn_step]

C2D cold bug? You left a NOT out of there right?

yeah didn't you know?

[agenda2005]

Also i was kidding couse you put 4x512MB no 4x512kb as it should be

do you know how much ipc improoved from p4 to c2d?

why cant amd improove 25%? time will tell im not making up i got this info from the same person that told me 9 months before that:

C2D would kill amd
C2D would have cold bug
C2D would get over 3.6GHz OC

so i trust him

Alright, thanks for the correction. I will wait and see what AMD can bring to the table.

[Lightman]

Another FUD spreaded by Fuad
Common, die shoot of K8L/K10 shows that each core L2 cache is surrounded by logic, so AMD can't do anything with it. The only cache which can be expanded is L3 and even AMD is stating clearly in leaked documents about that. So this 'news' is FUD or he mixed L2 with L3 cache .