K8l to have 6mb cache

[onewingedangel]

I have not seen anything about k8l having a 4 channel memory controller, or 2 dual channel ones. From my understanding k8l will plug into s1207 boards that are wired for dual channel, and whilst it would be possible for channels to be disabled for this purpose, it doesn't suggest there would be 4 channels, thus I'd put forward that there is a dual channel memory controller until proven otherwise.

Secondly where are these IPC numbers coming from? We don't know how much faster k8l will be clock for clock.

It seems almost definate that k8l will be a 4 issue design, so theres up to 33% improvement from that alone. I'm willing to bet there going to be some other small changes as well, but improving IPC is not something that you can do easily, and its not a task that scales linearly with the number of transistors your able to throw at the task. Taking into consideration your suggestion of20% higher IPC than kentsfield (which is optimistic):

3000 x 1.2 = 3600

If k8l was 20% faster clock for clock, it would take a 3.6ghz kentsfield to match a 3ghz k8l. AMD are aiming at 2.7-2.9ghz and traditionally amd don't leave much headroom on their high end parts.

You could buy a kentsfield today, overclock it and get k8l level performance. A year from now intels offering will have larger cache and faster fsb to keep the core fed, have a new chipset with a ddr3 memory controller, and possiby higher IPC with things like sse4 added to potentially speed thing up further.

I think the two will be very close on IPC, not a 20% difference at least, and intel will be clocked at least 20% higher stock, and have more headroom for overclocking.

[arisythila]

I don't think it's impossible that AMD may produce the variant of the QC part with 1MB dedicated L2 per core,but i think they evalueted pros and cons and are aiming for the best perf./$ option.Maybe for the server market ,highest number part will have larger L2.
With new IMC and high speed DDR2 next year,i think the New Core will do great against intel York/Wolf variants(i really believe c2d wouldn't be a match for it-for Dual Core part that is;Kents will have a hard time too since the shared FSB)

I also think the new core will do great... I also think AMD isnt afraid to let Intel have the lead for awhile. Intel is in a race... AMD is just trying to make a great processor.

~Mike

[arisythila]

Limited reading skills seem to be a problem for you.

Intel has REPEATEDLY stated that there will be a NEW architecture every 2 years. That means at the WORST a core shrink only next summer for C2D and a new architecture the summer after that.

That is an absolutely BLISTERING pace for AMD to keep up with.

I don't think so.. AMD is still growing, Intel has already grown. I also dont think AMD cares if Intel is ahead. Time will tell ofcourse. :-)

~Mike

[onewingedangel]

try loading a kentsfield with 4 different apps that calculate a lot of data and are not multithreaded, then repeat the same with just one of the apps, then you will see how much kentsfield is loosing

Um, is the answer half its l2 cache?(1 core accessing 4mb as opposed to 4 cores on 2 dies accessing on average 2mb each). The conroe dies shared l2 allows the full 4mb to be given to one core, so you could say its a gain of extra cache when using only 1core as opposed to a loss when multitasking, as a discrete l2 design wouldn't allow the core to get the extra cache. When running 4 apps its not neccesarily the fsb that proves the bottleneck. 50% extra cache for the 45nm core 2 variants should help out on this score.

[metro.cl]

As far as i know K8L will have 25% faster IPC that Core 2 Duo. It all will dependo on how high AMD can clock them

[Shadowmage]

There are some SERIOUS logical fallacies that need to be addressed here:

1) AMD's estimated 40% IPC improvement for K8L over K8 included the estimated improvement in gate switching from SiGe. So there is no 40+40+40 that the AMDroids would want everyone to believe. It is simply ONE estimated 40% (and that was just a number tossed out by NN, so it has to be taken with a HUGE grain of salt until verified by some hard numbers).

I don't know about the other points, but you're obviously misinformed about the definition of IPC. IPC stands for "instructions per clock", meaning the average amount of instructions a processor can complete every clock cycle. Therefore, IPC is independent of the clock cycle. Anyways, given the improvements, a best-case 40% IPC improvement over K8 is not unreasonable at all.

[madcho]

i think that core will be 4*1MB L2 + 2MB L3. It will start in Q3 one Quad father. on L1FX+ with HT3, and DDR2@1066

AMD will release Barcelona first in H1 ( AMD press service told me ). Barcelona is for 1207, and AMD will release special Barcelona for Quad father. 4*512MB L2 + 2MB L3.

Don't cry because we can't use HT3 @ start. HT3 i very useless for moment HT2 for moment is not used to the maximum.

Next chipset's will be more higher clocked for HT2 i think. Ati can release very easely one chipset @ 1.5ghz even more.

I recommand to all who are waiting for a great product from AMD, to buy the X4 @ lunch and wait for DDR3 before any change.

Remember that HT3 is very useless for moment.

[Sparky]

IMO....

If intel has the lead for awhile, so be it. I've never had a top of the line CPU so I don't really care much. AMD makes plenty fast CPUs for most things now, and if K8L is that much faster than K8 it will be awesome. Just because intel's chips may do better in benchmarks doesn't mean there will be that much difference in real life usage. Only purpose of those better benchmarks are for bragging rights

My

[Turtle 1]

I got this at the inquirer also. Read it there is one statement that got my att. See if it gets yours. Because of that statement. K8L has to be a 4 issue core. Or the afore mentioned statement is completely false. I don't know if true or false. Only that its very interesting.

http://www.theinquirer.net/default.aspx?article=36017

As for Yorkfield being native or not. I believe the other reports that are out . Which all stem from IDF or the same timeframe. NO eirlier or latter sources. York will have Shared L2 cache among all 4 cores. If that = Native it will be native . If that = something else thats what it will be. If all the reports are correct about york . the best we will see is a 10% improvement in performance.Clock for clock

If Inquirer got it right on this link . York will be slower than K8L. I personnlly don't care which it is. I am more interested in who is putting out the more informed info. So we all can recognize and expuse more aeg members.

[metro.cl]

Is this the one you are referring to?:

Under IPC Enhanced Cores
- Up to 4 Double Precision FLOPs/cycle

That does NOT mean a 4-issue core. That means either FOUR FPU units or TWO double pumped FPU units.

3/4-issue terminology is referring to the instruction decoders, not the floating point units.

ok the info i got long time ago is mostly:

that k8l will have 2x256kbit FPUs

but real k8l (at that time only one k8l existed)

[Turtle 1]

Is this the one you are referring to?:

Under IPC Enhanced Cores
- Up to 4 Double Precision FLOPs/cycle

That does NOT mean a 4-issue core. That means either FOUR FPU units or TWO double pumped FPU units.

3/4-issue terminology is referring to the instruction decoders, not the floating point units.

Ya that was the one . . What is that 300% improvement over k8. I would think that 4 issue core would be required or it would be bottlenecked.

[vitaminc]

I don't know about the other points, but you're obviously misinformed about the definition of IPC. IPC stands for "instructions per clock", meaning the average amount of instructions a processor can complete every clock cycle. Therefore, IPC is independent of the clock cycle. Anyways, given the improvements, a best-case 40% IPC improvement over K8 is not unreasonable at all.

uh, if you double the number of cores, the IPC should also double, aight?

and if you are talking about K8 vs K8L cores, 40% IPC improvement is not unreasonable but still pretty far fetched.

[madcho]

Is this the one you are referring to?:

Under IPC Enhanced Cores
- Up to 4 Double Precision FLOPs/cycle

That does NOT mean a 4-issue core. That means either FOUR FPU units or TWO double pumped FPU units.

3/4-issue terminology is referring to the instruction decoders, not the floating point units.

Don't think so. The number of decoder is not the number of issue that i heard.

AMD X4 will have four complexe decoder, easy to see it on die shot, even on the low res die shot.

I think that the number of fetch, is the number of issue. AMD don't go to 4 fetch, but the fetch will be 32bits instead of 16 bit of deep.

AMD may transphorm some simple instructions in one complexe. I think so. If any body have some news more fresh

thx

wait & see

[Turtle 1]

Turtle - I'm not seeing 300% in anything in that article. Am I missing something?

This is from the article
It also supports dual 128-bit SSE date flow, dual 128 bit load per cycle,

What does k8 have. 64-bit SSE date flow. If this info is correct thats a 300% improvement.

[nn_step]

You would need "double Fetch" which K8L just happens to have
not a 4th integer stage

[BlackX]

while reading the posts I was hoping somehow not to see C2D named.. but this time is not an exception..

INQ is like broken phone. Collects pieces of rumors and puts all together.

[madcho]

what about integer in X4 ? I don't read anything about the question

[nn_step]

K8L has 3 complex integer, in contrast to Conroe's ONE complex integer unit

[[XC] Teroedni]

while reading the posts I was hoping somehow not to see C2D named.. but this time is not an exception..

INQ is like broken phone. Collects pieces of rumors and puts all together.

Or even creates the rumor itself.
It should be forbidden to link to the Inquirer.
At least half of what them post is bull.
But then Turtle 1 would perhaps have to little to do

[agenda2005]

This thread is about the amont of cache on K8L.

AMD's own words on this is 4x512kB L2 and 2MB L3 cache that is expandable, Maybe 3MB, 4MB .....

This is primarily because AMD knows quite well that cache increase gains very little for K8 architecture. Sempron with 256kb L2 are doing well against FX with just as little as 100- 150MHz clock differential.

The anandtech article linked by brentpresley explain most of the needed improvements for K8--> K8L to be more competitive.

It's quite amusing to see people counting their eggs about what K8L will do. Some said 25% higher IPC, some even say 40 + 40 + 20 which is rather silly.

The truth is that AMD will continue to perfom simulation about the expected performance of K8L on paper design, but usually, the tape out product will give a completely diffent result. Therefore any IPC improvement over K8 now is pure speculation at best.

While I would prefer to restrain myself from mentioning anything about Core 2, but I felt it would be rather boring not to do so.

Core 2 architecture for now we know and can buy the product on the open market. Intel actually restrained themselves from predicting what IPC improvement we would get until the product was finished and tested.

All these K8L IPC speculations are pure marketing propanganda and BS to keep AMD customers, especially the server ones happy and hopefull.

The truth is that, K8L or whatever it will be called is still going to be 3 issue Core with a lot of core improvement. This will not change things drastically against Core 2 archtecture that have potential clock headroom aside from boosting a strong OoO execution units, aggresive prefetching and huge cache estate.

Thanks to brentpresley for pointing out the FSB issue with kentsfield. Yes,It's true that Core 2 architecture max out at about 3.4-3.5GHz on the FSB. That's alot of headroom for Intel before DDR3. Core 2 prefecthers are very aggressive and therefore have little use for an on-die memory controller. An on-die MC on Core 2 will be an added bonus, but not anything to be eager about.

There are still quite a lot of tweaking that Intel is doing on the Core 2 architecture and that should make AMD be aware that they have a long way to go.

EDIT: For spelling

[metro.cl]

This thread is about the amont of cache on K8L.

AMD's own words on this is 4x512MB L2 and 2MB L3 cache that is expandable, Maybe 3MB, 4MB .....

This is primarily because AMD knows quite well that cache increase gains very little for K8 architecture. Sempron with 256kb L2 are doing well against FX with just as little as 100- 150MHz clock differential.

The anandtech article linked by brentpresley explain most of the needed improvements for K8--> K8L to be more competitive.

It's quite amusing to see people counting their eggs about what K8L will do. Some said 25% higher IPC, some even say 40 + 40 + 20 which is rather silly.

The truth is that AMD will continue to perfom simulation about the expected performance of K8L on paper design, but usually, the tape out product will give a completely diffent result. Therefore any IPC improvement over K8 now is pure speculation at best.

While I would prefer to restrain myself from mentioning anything about Core 2, but I felt it would be rather boring not to do so.

Core 2 architecture for now we know and can buy the product on the open market. Intel actually restrained themselves from predicting what IPC improvement we would get until the product was finished and tested.

All these K8L IPC speculations are pure marketing propanganda and BS to keep AMD customers, especially the server ones happy and hopefull.

The truth is that, K8L or whatever it will be called is still going to be 3 issue Core with a lot of core improvement. This will not change things drastically against Core 2 archtecture that have potential clock headroom aside from boosting a strong OoO execution units, aggresive prefetching and huge cache estate.

Thanks to brentpresley for pointing out the FSB issue with kentsfield. Yes,It's true that Core 2 architecture max out at about 3.4-3.5GHz on the FSB. That's alot of headroom for Intel before DDR3. Core 2 prefecthers are very aggressive and therefore have little use for an on-die memory controller. An on-die MC on Core 2 will be an added bonus, but not anything to be eager about.

There are still quite a lot of tweaking that Intel is doing on the Core 2 architecture and that should make AMD be aware that they have a long way to go.

EDIT: For spelling

that is like 130392920% improovement

[Turtle 1]

K8L has 3 complex integer, in contrast to Conroe's ONE complex integer unit

NN you know full well that comment . Would raise a few eyebrows. You must be a good fisherman.

[Lightman]

Another FUD spreaded by Fuad
Common, die shoot of K8L/K10 shows that each core L2 cache is surrounded by logic, so AMD can't do anything with it. The only cache which can be expanded is L3 and even AMD is stating clearly in leaked documents about that. So this 'news' is FUD or he mixed L2 with L3 cache .

[agenda2005]

that is like 130392920% improovement

You can speculate whatever you like, but making up for 20% lag is quite a lot in the CPU world.

Time will tell, but your 25% IPC improvement of K8L over Conroe is too ambitious IMHO. That is approximately 45% improvement per clock over K8. AMD will have to come out with a perfect design that will fill up the CPU pipeline and extensively utilize the 3 wide issue.

Even Core 2 with its OoO and aggresive prefetchers is only able to sustain one issue per clock cycle. Aside from that Core 2 also have potentially higher clock to execute instructions.

Go and read up man. AMD have their work cut out for them.

[Turtle 1]

Or even creates the rumor itself.
It should be forbidden to link to the Inquirer.
At least half of what them post is bull.
But then Turtle 1 would perhaps have to little to do

Acually since 3 this morning I have read a lot. Visted my favorite forum. Assembled to C2D water cooled gamers. Installed software. prepared for shipping. So all and all been pretty busy this day.