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If it does have 6MB cache, my moneys on 4x512k L2 + 4M L3.
Having total l3 equal total l2 would be bad enough, but having more l2 than l3 would be retarded (I know AMD's cache scheme is not inclusive, but the speeds are still tiered - so more 'faster' L2 would be prefered, so 4x1m l2 would be better than 4x512 + 2mb l3 where all cores are in use (if a single core uses all l3 then obviously that may be different).
However, if amd are using the l3 just to store the data that would be worked on by multiple cores, so each l2 stores the data that the core works on, and the l3 is used to ease intercore communication - not boost single core performance, then 4x1m + 2m l3 would be the better option - even though the 'shared cache' wouldn't boost performance when only one core is in use.
Last edited by onewingedangel; 11-28-2006 at 03:35 AM.
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