i wrote it
the parser is written according to the jedec ddr2 spd specification. once the program works more stable i will add ddr1 support
i wrote it
the parser is written according to the jedec ddr2 spd specification. once the program works more stable i will add ddr1 support
Thanks for sharing !Originally Posted by W1zzard
ATM I have no DDR2, so I won't be able to do some testing![]()
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Is this something i can use to rewrite my OCZ SPD so instead of booting at 5-6-6-18 it can boot up at 4-4-4-15 like they are supposed to??? on my P5W DH Board at 2.1vOriginally Posted by W1zzard
When i put SPD controlled memory i get 5-6-6-18 with 42 TRef and the other value at 7(Dont remember wich), if i put it manually, the subtimings move also, to 37 instead of 42 and 6 instead of 7, wich then my computer would only boot at 266FSB.
DUH!!! i don't even understand my self.![]()
Last edited by pancito; 11-17-2006 at 03:05 PM.
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