Vector processing on nehelam?

[Turtle 1]

let me explain it this way
SSE, SSE2, SSE3...SSEn
http://en.wikipedia.org/wiki/Streaming_SIMD_Extensions
Do Floating point and SIMD math (aka vector)
http://en.wikipedia.org/wiki/SIMD
By seperating the Floating point math unit from the Vector unit, they can massively improve performance for BOTH.
Since the Floating Point Unit can specialize for Floating point math (and not have to worry about vector math)
And the Vector unit, only has to deal with Vectors.
Now Altivec/VMX (depending on who you ask [Motorola or IBM])
Basically does exactly that.
Now what I am hoping for is that they follow the Altivec design, which is VASTLY superior to ANY Intel/AMD Streaming SIMD Extension

Nice links nn. Now if I understand this correctly . Vector units to operate efficiently need there own registor. True or False. Is it possiable that the russian company intel bought a while back. Will aid intel with a much better compiler that could overcome FFU and vector units trying to use the register at the same time ? Anyone!

[nn_step]

Nice links nn. Now if I understand this correctly . Vector units to operate efficiently need there own registor. True or False. Is it possiable that the russian company intel bought a while back. Will add intel with a much better compiler that could overcome FFU and vector units trying to use the register at the same time ? Anyone!

Ideally speaking you would want 32 registers JUST for the Vector Unit. 128 or 256 bits wide apiece.
Which will cause a Double in the space needed for Floating point/Vector math But you will get up to (in theory) 4 Times the processing power. Which SHOULD make it a Floating point/Vector Monster