Quote Originally Posted by ozzimark
i thought having command rate at 2T meant two clocks from the last command
At 2T the minimum command-to-command spacing will be two address bus timeslots, so the way I see it you thought right. At 2T, each address is held valid for two cycles, and qualified by the chip select signal on the crossing of the second clock. So there'd be a rest period on the bus, but each command/signal would still occupy two clocks on the controller, which naturally causes a delay, and hightens the risk of command collisions.