Quote Originally Posted by _damien_
Not that I think the row sensing actually completes in one single cycle, but on a rig where the command rate is locked at 2T, we'll never be able to find out for sure because the tRCD-delay is 2 clocks in reality. As I said earlier, the row signal will get a 2-cycle "rest period" before the memory starts responding to the read command. There'll be no data corruption unless the CAS operation is triggered too early, which is impossible (assuming the row signal always stabilizes in 2 clocks).
i thought having command rate at 2T meant two clocks from the last command