Conroe 2.4Ghz on 965G mobo, brief test...

[agenda2005]

Tim,
The version 9 of the intel compiler also allow optimization for AMD 64 as well. I'm not sure if their's new version of the compiler that have compilation flags for Macro op fusion that allows an extra instruction issue.

The 128-bit SSE on Conroe will obviously benefit more than AMD 64 because two 64-bit SSE(x) intructions will now require one cycle unlike two in Presscott and Athlon 64. This is nobody's fault since Intel have concentrated more effort on making better CPU than crippling competitors performance on their compiler.

You guys should be able to get a Conroe sample from Intel if you ask. Just write a request and give your website link as well as other link to websites using your benchmark.

In the meantime, You can make an SSE/SSE2/SSE3 compiled binary for Victor to install Windows Server 2003 to test the power of Conroe. It will sure be interesting to see how that bad boy will do.

Conroe/Woodcrest will surely be the new king for Molecular Dynamic Simulation developers. This will also reflect well on their SPEC results.

[Donnie27]

Tim,
The version 9 of the intel compiler also allow optimization for AMD 64 as well. I'm not sure if their's new version of the compiler that have compilation flags for Macro op fusion that allows an extra instruction issue.

The 128-bit SSE on Conroe will obviously benefit more than AMD 64 because two 64-bit SSE(x) intructions will now require one cycle unlike two in Presscott and Athlon 64. This is nobody's fault since Intel have concentrated more effort on making better CPU than crippling competitors performance on their compiler.

You guys should be able to get a Conroe sample from Intel if you ask. Just write a request and give your website link as well as other link to websites using your benchmark.

In the meantime, You can make an SSE/SSE2/SSE3 compiled binary for Victor to install Windows Server 2003 to test the power of Conroe. It will sure be interesting to see how that bad boy will do.

Conroe/Woodcrest will surely be the new king for Molecular Dynamic Simulation developers. This will also reflect well on their SPEC results.

Some of the folks here didn't read the link. It showed how Conroe processes 128Bit SIMDs in ONE CYCLE, not two as P4 and A64 does.

[uOpt]

The 128-bit SSE on Conroe will obviously benefit more than AMD 64 because two 64-bit SSE(x) intructions will now require one cycle unlike two in Presscott and Athlon 64. This is nobody's fault since Intel have concentrated more effort on making better CPU than crippling competitors performance on their compiler.

Just for clarifications: SSE3 always has 128 bit instructions. On earlier platforms they might need more cycles to execute but the 128 bit instructions as such are present in any processor supporting SSE3.

I don't think it is quite correct to say that two 64 bit SSE operations will now require half the time. This is only the case when ...

• ... there are indeed independent units to compute. Doing two instructions at the same time requires that non depends on the outcome of the other. That is frequently not the case
• .... and unless it is hand-coded assembly the compiler has to be sure about the previous fact. It can be nontrivial for the compiler to figure this out in a bulletproof way. If the compiler is not entirely sure it will default to be conservative
• ... to be most effective the compiler has to be able to do out-of-order processing to scrap two 64 bit operations into one 128 bit one even if they are at different places in the source code. Prooving that this is safe is nontrivial, too, in particular in languages like C/C++ where there is a lot of aliasing going on

[agenda2005]

Just for clarifications: SSE3 always has 128 bit instructions. On earlier platforms they might need more cycles to execute but the 128 bit instructions as such are present in any processor supporting SSE3.

I don't think it is quite correct to say that two 64 bit SSE operations will now require half the time. This is only the case when ...

• Agreed, but that is usually the case for highly vecorized codes like MolDyn, BLAS and LINPACK. Two 64-bit SSE and SSE2 instructions can be fetch and decode in one cycle instead of one( As in A64 and Prescott) and the code scale according to the degree of vectorization.
  
  

• ... there are indeed independent units to compute. Doing two instructions at the same time requires that non depends on the outcome of the other. That is frequently not the case

[incurable]

You guys should be able to get a Conroe sample from Intel if you ask. Just write a request and give your website link as well as other link to websites using your benchmark.

I believe Intel would rather not send free samples to AMD or any of its personnel.

[agenda2005]

I believe Intel would rather not send free samples to AMD or any of its personnel.

There might be some elements of 'truth' in that. I remember when the ScienceMark writers were alleged to have written the program to show the power of Athlon back in the days of AXP and Northwoord. They seems to have changed now, but that allegation might still hurt them.

http://sharikou.blogspot.com/

came across this blog stating about how a a64 could easily beat conroe...
is there any truth to it???

That looks like a speculation at the moment.

When Conroe is compiled with SSE/SSE2/SSE3/SSE4 optimizations, then we shall know the real truth.

The guy have no clue that the ScienceMark benchmark was running on plane Jane x87 which does no good to current days CPUs.

SPEC score will clear up those gray areas. There are more than 20 benchmark suit in SPEC and each of them uses > 100MB of memory.

[incurable]

There are some element of 'truth' in that. I remember when the ScienceMark writers were alleged to have written the program to show the power of Athlon back in the days of AXP and Northwoord. They seems to have changed now, but that allegation might still hurt them.

The truth is that Tim Wilkens, the guy who programmed the apps this benchmark is based on (for his PhD research, IIRC), scored a job w/ AMD after getting his degree.

Now don't get me wrong, I'm not saying that Tim (I don't even know if he's still actively involved in the project.) or Alex or the others who are part of ScienceMark group are writing their software in a way to show one competitor scoring higher than the other. But instead of sending the ScienceMark guys pre-release hardware, Intel could just mail it to Hector himself.