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Thread: T or N in corner, what does it mean?

  1. #51
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    Ok you want info heres info. From my gathered results this is what i have come up with.

    *EDIT* wanted to add that in my search I found that bottom line and top line chips fared best. Mid line chips did OK but not spectacular.

    LDBHE = cold bug free

    N on wafer= Low voltage higher clocks/lower temps to a certain point/possible death clocked high w/high volts (24/7 use) high volts = 1.6-1.65

    T on wafer= High voltage higher clocks/higher temps/possible death clocked high w/low volts (24/7 use). low volts = 1.4-1.45

    Week
    Ive found the first weeks to be best

    for instance 0501, 0601, and so on. 0551 works also but it appears that the actual first week is the creme of the crop.

    Highest OC steppings are higher last 4 2nd line.

    RPMW low
    SPMW moderate
    TPMW medium
    UPMW normal
    VPMW high
    XPMW Highest

    Batch # in the 0030 and lower would be better yields but not necessarily in the sense of HIGH OC, the difference can also be a stronger mem controller or higher over all HTT.

    Once again this is all in theory and FYI has been compiled with over 1000 cpu results from users here.

    Now with all this compiled I went on a stepping hunt. I ended up with this stepping based on the equipment i have in my possesion.


    E4 revision X2 3800
    LDBHE 0601 XPMW
    batch # 60017
    T chip

    and the results are here.....This isn't maxxed yet either as it was more of a test run for my DI tube and manta versus anything else.
    http://valid.x86-secret.com/show_oc.php?id=79315
    Last edited by chew*; 03-18-2006 at 03:15 PM.
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  2. #52
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    Quote Originally Posted by afireinside
    Of course I wouldn't. Two things though:

    1:He doesn't hide silly things (I'm sure the meaning of "T" and "N" won't cause a revelation)

    2:I wouldn't go around blabbering "I KNOW ALL OF JASONS SECRETS AND TWEAKS FOR RECORDS AND JUST ABOUT EVERYTHING ELSE BUT I CAN'T TELL YOU SORRY HAHA" even if you're not making a thread about it you're still pissing people off by saying you know what it means but you can't say. And I'm not the only one that doesn't like it.
    What makes you so sure the meaning of T vs. N is silly? And FYI I don't go around "blabbering" that I know info and can't tell. I was asked directly and I responeded accordingly. Why should anyone be pissed? I guess you should be mad at the world since EVERYONE probably has some info which you don't . When you get trusted with info that's NDA, maybe that's when you'll know what I mean (or maybe not).

  3. #53
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    Quote Originally Posted by chew*

    for instance 0501, 0601, and so on. 0551 works also but it appears that the actual first week is the creme of the crop.
    Where did you see an 0501 LDBHE?????

  4. #54
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    Quote Originally Posted by s7e9h3n
    Where did you see an 0501 LDBHE?????
    About 3 months ago when i stated searching. I can't remember the chip. I know the poster claimed no coldbug.
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  5. #55
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    Quote Originally Posted by chew*
    About 3 months ago when i stated searching. I can't remember the chip. I know the poster claimed no coldbug.
    If you could, please try to get the cpu info for me

  6. #56
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    Quote Originally Posted by s7e9h3n
    What makes you so sure the meaning of T vs. N is silly? And FYI I don't go around "blabbering" that I know info and can't tell. I was asked directly and I responeded accordingly. Why should anyone be pissed? I guess you should be mad at the world since EVERYONE probably has some info which you don't . When you get trusted with info that's NDA, maybe that's when you'll know what I mean (or maybe not).
    If I did know something under NDA I wouldn't publicly anounce that I knew it. If someone personally asked me I'd tell them I'm not allowed to talk about it. Simple as that. I'm done.
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  7. #57
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    Quote Originally Posted by afireinside
    If I did know something under NDA I wouldn't publicly anounce that I knew it. If someone personally asked me I'd tell them I'm not allowed to talk about it. Simple as that. I'm done.
    I guess when I said 'No Comment', that must have meant "I KNOW ABOUT THIS SECRET AND I'M NOT TELLING"

  8. #58
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    Quote Originally Posted by dogsx2
    : I have really never liked the "I know but I'm not telling." Why tell us you know something if your not going to tell us? If it's a secrect, why not keep it to yourself instead of I know a secrect but am not telling? I'm not trying to be harsh with you, just asking questions. If you feel it is harsh, just go ahead and me .
    YES!!!!! and that's why i like you

    either don't say a word or say what it is..........hinting just doesn't do it for me either
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  9. #59
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    @s7e9h3n,

    How about passing that information to someone that is not under NDA? I don't think that only one person at AMD knows the meaning of "T" and "N" placed on the CPU package (substrate) - I would even think it has to be some sort of common knowledge among their engineers - so If "your friend" knows, then ask him to tell you that and then you relay it to someone that has nothing to do with AMD or any NDA. So in the end, neither you nor anyone else close to you can be linked to "leaking" this information...
    Last edited by bachus_anonym; 03-18-2006 at 03:04 PM.

  10. #60
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    Quote Originally Posted by chew*
    Ok you want info heres info. From my gathered results this is what i have come up with.

    LDBHE = cold bug free

    N on wafer= Low voltage higher clocks/lower temps to a certain point/possible death clocked high w/high volts (24/7 use) high volts = 1.6-1.65

    T on wafer= High voltage higher clocks/higher temps/possible death clocked high w/low volts (24/7 use). low volts = 1.4-1.45

    Week
    Ive found the first weeks to be best

    for instance 0501, 0601, and so on. 0551 works also but it appears that the actual first week is the creme of the crop.

    Highest OC steppings are higher last 4 2nd line.

    RPMW low
    SPMW moderate
    TPMW medium
    UPMW normal
    VPMW high
    XPMW Highest

    Batch # in the 0030 and lower would be better yields but not necessarily in the sense of HIGH OC, the difference can also be a stronger mem controller or higher over all HTT.

    Once again this is all in theory and FYI has been compiled with over 1000 cpu results from users here.

    Thank you

    Interesting though. We already knew that low batch numbers were best and that "BH" didn't bug. First week also makes sense since my 3000+ DTR 0501 chip was an absolute monster doing 2.95ghz on ice water.

    My 170 is an "N" XPMW though and it can't even do 3ghz on ice water. It also needs 1.75v for high clocks. I've had a 3700+ "N" chip that required 1.8v to reach it's max clocks.

    This seems like a good guide line but I still feel it's a lot of luck in the end.
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  11. #61
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    Quote Originally Posted by chew*
    Just wow at that overclock. 350 HTT is rock.

    I got 356x9 but not 360x8 on SS, so that's a better chip I think.

  12. #62
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    Quote Originally Posted by dinos22
    YES!!!!! and that's why i like you

    either don't say a word or say what it is..........hinting just doesn't do it for me either
    Sorry to say, but that's just an excuse to be lazy. Some info is out there, you just have to gather it and do the research yourself. When I decoded the stepping on the A64, no help was given to me by any "insiders". It was basically a tedious process which involved anylizing the info on hundreds upon hundreds of cpu's. Obviously, Chew looks to be doing the same for his own purposes. You're entitled to your own opinion, but please don't expect information to be just handed to you just because you requested it.

  13. #63
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    As i said this is not LAW this is just compiled results from over 1000 cpu's.

    Also anyone ever remember the story about the hen that plowed the field,planted seeds,watered the field , harvested the corn, husked the corn, ground the corn, made flour then baked the bread and no one helped her do any work but when the bread was done everyone wanted some........

    This may be why some people don't like to share info.
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  14. #64
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    Quote Originally Posted by bachus_anonym
    @s7e9h3n,

    How about passing that information to someone that is not under NDA? I don't think that only one person at AMD knows the meaning of "T" and "N" placed on the CPU package (substrate) - I would even think it has to be some sort of common knowledge among their engineers - so If "your friend" knows, then ask him to tell you that and then you relay it to someone that has nothing to do with AMD or any NDA. So in the end, neither you nor anyone else close to you can be linked to "leaking" this information...
    Cmon michal, you can't be serious, can you? It's kinda like if you're not caught stealing, then it's OK?

  15. #65
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    yeap you got me i'm just lazy
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  16. #66
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    chew* that`s A LOT of work you done combining every possible info and just telling it to all ppl here in short clear statements.
    Appreciate it man

  17. #67
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    thanks for the results chew*, good to see members supporting my own opinions about others too.

    If you got info share it, or if you cant, dont say a word about it, it just entices people to spam a thread, pestering for that info.

  18. #68
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    Quote Originally Posted by shuRe
    thanks for the results chew*, good to see members supporting my own opinions about others too.

    If you got info share it, or if you cant, dont say a word about it, it just entices people to spam a thread, pestering for that info.
    Thank you for re-inforcing the reason why I didn't want to post here anymore. I'll leave you all to all your theories and such. This is where my XS stint comes to an end.......

  19. #69
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    Quote Originally Posted by s7e9h3n
    Sorry to say, but that's just an excuse to be lazy. Some info is out there, you just have to gather it and do the research yourself.
    oh really? so if you can afford to spend your time to do such things you assume everyone else can too?

    for chew*.
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  20. #70
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    I also want to thank all those that helped me in my 3 month long analysis. O wait there is no one to thank but myself............. actually I can thank stephen and FCG for there work on the cold bug.

    Just for the record I DON'T have the TIME. I MADE the TIME.
    Last edited by chew*; 03-18-2006 at 03:55 PM.
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  21. #71
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    right, tell me about that, when someone steal the theory of AMD stepping and no cold bug or n&T stuff and sounds he is the first one to figure out that?
    Give me a break.
    T or N..that 's what I told initially, and oh ya, there are lot more I bet you don't know. No matter Steve call me and said

    He is done for XS.

    And I will see who gets AM2 first.
    Last edited by Onepagebook; 03-18-2006 at 03:53 PM.

  22. #72
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    Actually i didn't steal it OPB. In fact i helped steve on it and compiled results in a thread for him to prove his theory........Alot of the other stuff i deduced on my own. And once again this is just theory I could well be wrong as there are alot of factors that i can't calculate in such as the user behind the PC. We all know that Overclocker A might not be able to run a CPU as high as Overclocker B.

    If I take credit on anything it's for the fact that i compiled this for 3 months and thats all.
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  23. #73
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    oh ya? at least you should have my permission to post the pic of "my" CPU.

    http://www.xtremesystems.org/forums/...11&postcount=8

  24. #74
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    permission you guys have a serious problem

    YOU ARE POSTING ON A PUBLIC FORUM....................
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  25. #75
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    Quote Originally Posted by Onepagebook
    oh ya? at least you should have my permission to post the pic of "my" CPU.

    http://www.xtremesystems.org/forums/...11&postcount=8
    Well thats not your cpu....Didn't you kill it........ That is your cpu's little brother from what I was told and a cpu that i am attempting to aquire...............through stephen and he sent me the pic......... I don't think steven is mad at me OPB.........Maybe he is if so have him PM me......
    Last edited by chew*; 03-18-2006 at 04:12 PM.
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