AMD Stepping Information Decoded

[Cpt Twitchy]

I am soo lost but thanks. Maybe when I am at a higher functioning level I will try to figure this out again.

[chew*]

Ok heres what he's saying In plain english.......I have a LDBHE x2 3800 Known good under phase. now according to his chart BH on my cpu is the memory controller identifier. This means the chances of playing in the cold with BH stepping chips is greater than others as that version of memory controller wasn't as bugged as others.

So far my personal database from searching the forum came up with these as the better chance chips.
I will do more searching in a while

BH, BW, B2

[Cpt Twitchy]

Thank you chew. Makes more sense now.

Time to get back to football game.

[s7e9h3n]

hmmm, yes.. i smell a new database coming on

crash, i'm gonna venture CCBHE

I'm gonna go out on a limb and say a CCBHE FX60 won't be in the works for two reasons:

1. It's a version of the memory controller that seems to support only 1MB of L2 cache TOTAL. Past cpu's which have this stepping have ONLY been single-core San Diegos or 2x512K L2 Cache Manchesters. In fact, from observations, it looks as if AMD may have stopped producing Manchester cores all together as most, if not all, current 2x512K L2 cache cpu's are all Toledos (2x1mb cache w/ half the cache disabled).

2. AMD has moved much further down the road past the rev. BH memory controller and if everything stays according to plan, they won't create any new cpu's which revert back to this particular revision. A non-cold-bugged FX60 would have to be a brand-new revision which we haven't seen before since AFAIK, all the 2x1mb L2 Cache cpu's have a cold-bug to a certain degree.

There are a few things which are a mystery to me and quite possibly will never be answered - how does AMD "pick and choose" which revision memory controller makes it to production level? It's quite obvious that the memory controllers are designed long before the cpu's - that's why we don't see, for example, every rev. between BH and BW. AFAIK, there's no BK, BM etc. revisions on any cpu's. Those designs were most likely passed over in favor of revisions which we DO see -> BN, BQ, etc.....What changes are actually being made to the memory controller itself? If the reasons are able to be identified, then I'm sure the solution to the mystery of the cold-bug will follow closely behind. Also, in some instances, AMD has chosen to go with a revision of memory controller on certain cpu's and then go back to an "older" revision on subsequent cpu's. A good example is what happened with the a few FX57's (and maybe the s939 Opterons?)- Rev. BY cpu's were produced for a short time (OPB's CABYE 0524) and the revision which followed was CABNE (0528 and 0530). Why would AMD pass on a certain revision memory controller only to go back and produce it later?

Here's something I thought of while I was typing this Could it be possible the cold-bug may have something to do with a memory controller's ability to handle a certain amount of L2 cache? My reasoning is that there seemed to have been MUCH less of a problem with the cold-bug on cpu's with 1mb TOTAL L2 cache - be it a single, 1mb L2, or 2x512K L2. The problems in the cold became very apparent when the 2x1mb L2 cache cores appeared. I don't know of ANY non-cold-bugged rev. BW (CCBWE) cpu's and we all know how the CCB2E/CAB2E cpu's perform in the cold. Maybe the original design for the A64 memory controller only allowed for 1mb L2 cache to function properly in the cold and by tweaking it so now it can handle BOTH 1mb and 2x1MB L2 Caches, the result is a more severe cold-bug. I dunno....this is all speculation on my part

Well getting back to the original purpose of the thread, here are a couple more cpu's for your viewing enjoyment:

My FX55 Clawhammer - I still consider this, hands down, the strongest FX55 Claw I've ever seen. It was able to run @ 3ghz on a stock Opteron HSF 3dMark stable and not even break a sweat. (That was quite an accomplishment at the time). The memory controller on it was unbelievable - able to run a 28sec Spi1m @ 2900 on TCCD and garbage timings and as you all know.....no cold-bug to speak of:


My most recent dual core - ACBWE 4400+. Never tested on air - went straight to autocascade (before I had it modded for colder temps). Able to run dual Spi8m default speed @ 1.0Vcore. Cold-bugged @ ~-35 - -37C core temps.


I'll try to dig up a few more from my archives and show some more examples.....

[bachus_anonym]

There are a few things which are a mystery to me and quite possibly will never be answered - how does AMD "pick and choose" which revision memory controller makes it to production level? It's quite obvious that the memory controllers are designed long before the cpu's - that's why we don't see, for example, every rev. between BH and BW. AFAIK, there's no BI, BJ, BK, BL, etc. revisions on any cpu's. Those designs were most likely passed over in favor of revisions which we DO see -> BN, BQ, etc.....

What do you mean by that? Is that sentence true only to dual-core because we've seen Venice CBBLE or CBBID or Venus CABJE... The more I think about it the harder my feeling is that those two characters might not be exactly what you guys think... There is just gazzillion of combinations there on 90nm CPUs. It's just hard to assume that all of those are different revisions of memory controller... I think that there's something else in it... I don't know... Don't hurt me

EDIT: I smell that 3rd and 4th characters need to be treated separately...

[Cpt Twitchy]

What purpose does the Letters on the right side of the production week mean?

[s7e9h3n]

What do you mean by that? Is that sentence true only to dual-core because we've seen Venice CBBLE or CBBID or Venus CABJE... The more I think about it the harder my feeling is that those two characters might not be exactly what you guys think... There is just gazzillion of combinations there on 90nm CPUs. It's just hard to assume that all of those are different revisions of memory controller... I think that there's something else in it... I don't know... Don't hurt me

EDIT: I have a hinch that 2rd and 4th characters need to be treated separately...

You're right about those memory controller rev. I guess I was just thinking of the Diego cores when I was mentioning the ones when didn't exist Are you sure there's a Venus CABJE? Or did you mean CACJE? There's not quite a "gazzillion" revisions. I have a feeling if you sit down and list them, you'll be surprised at how few revisions there actually are - especially considering the broad range of cpu's they cover - from winnies, to venices, to clawhammers, to diegos, to x2's, to opties (both s939 and s940), and now to rev e6 diegos and venices......oh...and don't wanna forget about the s754 cpu's as well

Edit: Original post edited for truth :P

[s7e9h3n]

EDIT: I smell that 3rd and 4th characters need to be treated separately...

I thought of that, but couldn't come up with anything that was workable in terms of what they could mean. I had a hard time associating the "B" for example on a CBBLE with the "B" from a CCBWE. What's your reasoning behind your assertion?

The more I think about it the harder my feeling is that those two characters might not be exactly what you guys think.

EDIT: Once again, I have to state that this is all assumption and none of it may/may not be fact. I figure that an educated guess is better than none at all

[s7e9h3n]

What purpose does the Letters on the right side of the production week mean?

That's covered in one of the earlier posts

[bachus_anonym]

Are you sure there's a Venus CABJE? Or did you mean CACJE?

Yep, googled a bit and found Opteron 148 "CABJE 0551TPBW" listed at Trend4pc.de. It might be a mistake but that's all I know...
So far I think we've seen 3 variations of "3rd character": A, B and C and a plethora of options for the "4th" one... So that's why I kind of thought that maybe they both should be separated Don't ask me why, I'm just an innocent bystander here

[s7e9h3n]

Yep, googled a bit and found Opteron 148 "CABJE 0551TPBW" listed at Trend4pc.de. It might be a mistake but that's all I know...
So far I think we've seen 3 variations of "3rd character": A, B and C and a plethora of options for the "4th" one... So that's why I kind of thought that maybe they both should be separated Don't ask me why, I'm just an innocent bystander here

Ok, I'll edit the post again Yes, there are a number of options for the 4th character, but if you follow the memory controller revisions from the days of the Clawhammer, you'll notice that they move in somewhat of a logical pattern from A*x* to what is now C*x*.

Edit: Also, just a question about your theory. So are you saying that the 2 in say CCB2E somehow relates to the 2 in my Clawhammer (AAA2C) above? TBH, there really is no point trying to figure out the relationship between that 3rd and 4th character as it would only be useful if we knew what they actually represented. So realistically, we just have to take them for face value and assume there is some sort of correlation betweeen similar revision memory controllers.....

[kiwi]

Why not ask AMD what they mean?

[Cpt Twitchy]

That's covered in one of the earlier posts

I'll look for that but probably after the football games are over.

[zir_blazer]

The Memory Controller can't be more important that the rest of the Core itself to recibe a whole two letters to identify it. The third and fourth letter are probabily related to minor Core Revisions (Including but not limited to only the Integrated Memory Controller).
No idea about the first letter, because it alternately apears in a Processor with the same OPN in diferent manufacture dates (In the AuthScanner database, the Processor ADAFX53CEP5AT got AAASC 0352, SAASC 0352, AAASC 0402 and SAASC 0401 Steppings). Else, I would have pointed manufacturing process maturity, or maybe even silicon quality.

[chew*]

I'm gonna go out on a limb and say a CCBHE FX60 won't be in the works for two reasons:

1. It's a version of the memory controller that seems to support only 1MB of L2 cache TOTAL. Past cpu's which have this stepping have ONLY been single-core San Diegos or 2x512K L2 Cache Manchesters. In fact, from observations, it looks as if AMD may have stopped producing Manchester cores all together as most, if not all, current 2x512K L2 cache cpu's are all Toledos (2x1mb cache w/ half the cache disabled).

2. AMD has moved much further down the road past the rev. BH memory controller and if everything stays according to plan, they won't create any new cpu's which revert back to this particular revision. A non-cold-bugged FX60 would have to be a brand-new revision which we haven't seen before since AFAIK, all the 2x1mb L2 Cache cpu's have a cold-bug to a certain degree.

There are a few things which are a mystery to me and quite possibly will never be answered - how does AMD "pick and choose" which revision memory controller makes it to production level? It's quite obvious that the memory controllers are designed long before the cpu's - that's why we don't see, for example, every rev. between BH and BW. AFAIK, there's no BK, BM etc. revisions on any cpu's. Those designs were most likely passed over in favor of revisions which we DO see -> BN, BQ, etc.....What changes are actually being made to the memory controller itself? If the reasons are able to be identified, then I'm sure the solution to the mystery of the cold-bug will follow closely behind. Also, in some instances, AMD has chosen to go with a revision of memory controller on certain cpu's and then go back to an "older" revision on subsequent cpu's. A good example is what happened with the a few FX57's (and maybe the s939 Opterons?)- Rev. BY cpu's were produced for a short time (OPB's CABYE 0524) and the revision which followed was CABNE (0528 and 0530). Why would AMD pass on a certain revision memory controller only to go back and produce it later?

Here's something I thought of while I was typing this Could it be possible the cold-bug may have something to do with a memory controller's ability to handle a certain amount of L2 cache? My reasoning is that there seemed to have been MUCH less of a problem with the cold-bug on cpu's with 1mb TOTAL L2 cache - be it a single, 1mb L2, or 2x512K L2. The problems in the cold became very apparent when the 2x1mb L2 cache cores appeared. I don't know of ANY non-cold-bugged rev. BW (CCBWE) cpu's and we all know how the CCB2E/CAB2E cpu's perform in the cold. Maybe the original design for the A64 memory controller only allowed for 1mb L2 cache to function properly in the cold and by tweaking it so now it can handle BOTH 1mb and 2x1MB L2 Caches, the result is a more severe cold-bug. I dunno....this is all speculation on my part

Well getting back to the original purpose of the thread, here are a couple more cpu's for your viewing enjoyment:

My FX55 Clawhammer - I still consider this, hands down, the strongest FX55 Claw I've ever seen. It was able to run @ 3ghz on a stock Opteron HSF 3dMark stable and not even break a sweat. (That was quite an accomplishment at the time). The memory controller on it was unbelievable - able to run a 28sec Spi1m @ 2900 on TCCD and garbage timings and as you all know.....no cold-bug to speak of:


My most recent dual core - ACBWE 4400+. Never tested on air - went straight to autocascade (before I had it modded for colder temps). Able to run dual Spi8m default speed @ 1.0Vcore. Cold-bugged @ ~-35 - -37C core temps.


I'll try to dig up a few more from my archives and show some more examples.....

Steve what did that 4400 X2 do for stable clocks? and those 2nd line letters 2 and 3 would have scared me off.........Abbreviations for Cold Bug hehe

[ozzimark]

chew, why on earth did you quote all that?

and now to rev e6 diegos and venices......

what confuses me though, the E6 venice has a normal single core area, while i remember you showing a picture of the E6 san diego being a dual core with a single core enabled

also.. like i told you before, there MUST be something in there regarding the core as a whole. i think the 3+4th letters should be looked at together, but it pertains to more than just the memory controller, but the entire core.. which the memory controller is a part of.

last, before the recent sightings of the KAB3E san diegos, has anyone seen xxx3x before, be it A3 or B3?

[zir_blazer]

Those "San Diegos E6" or "Venices E4" are Toledos Rev. JH-E6 and Manchesters Rev. BH-E4 respectively, there is no mystery in them and actually, if you did the research, it never was. They're Dual Core Processors with one Core disabled.
Also, they retain the Stepping from the physical Core. Look around and you will find old Clawhammers with half of its Cache L2 disabled (For example, both the Athlon 64 2800+ ADA2800AEP4AP and the Athlon 64 3200+ ADA3200AEP5AP can come with the CAAMC Stepping), no surprise if this applies to Dual Cores as well even if we're talking about an entire Core disabled.

[ozzimark]

check what i said again, E6 venice, not E4..

[s7e9h3n]

chew, why on earth did you quote all that?


what confuses me though, the E6 venice has a normal single core area, while i remember you showing a picture of the E6 san diego being a dual core with a single core enabled

also.. like i told you before, there MUST be something in there regarding the core as a whole. i think the 3+4th letters should be looked at together, but it pertains to more than just the memory controller, but the entire core.. which the memory controller is a part of.

last, before the recent sightings of the KAB3E san diegos, has anyone seen xxx3x before, be it A3 or B3?

Check the stepping on the E6 Venice...It should tell you about the core Agreed that the letters may have something to do with the core, but still it's an unknown and I have a feeling the quality of the silicon can *possibly* be deduced from something in the third line.
The "K" series of processors probably follow the "C" series pretty closely as the "KAB2E"'s to the "CAB2E"'s. I'd imagine there are some "CAB3E"'s somewhere, it's just that we haven't seen them yet. AFAIK, there were very few, if at all any AAB2E's and the same would go for the AAB3E I would assume......

[zir_blazer]

check what i said again, E6 venice, not E4..

I'm talking for general clarification purposes before someone jumps on to incorrectly use Code Codenames. And no, this isn't "Semantic nonsense", I would say that "There is an HUGE diference!". Right, Locke?

[s7e9h3n]

Looks like there may be a possibility in the letter on the memory controller rev. i.e. A, B correlating to the physical core. A CAAZC Clawhammer 754 was just posted in the thread which I requested the cpu steppings. Could it possibly have to do with Die Size? A = .13, B = .9, and C = ?

[ozzimark]

Check the stepping on the E6 Venice...It should tell you about the core Agreed that the letters may have something to do with the core, but still it's an unknown and I have a feeling the quality of the silicon can *possibly* be deduced from something in the third line.
The "K" series of processors probably follow the "C" series pretty closely as the "KAB2E"'s to the "CAB2E"'s. I'd imagine there are some "CAB3E"'s somewhere, it's just that we haven't seen them yet. AFAIK, there were very few, if at all any AAB2E's and the same would go for the AAB3E I would assume......

hmmm.. the third line eh? i guess that would explain why there are variations between weeks with the same stepping.. perhaps lower 1st number/letter in the 3rd line is better.. my 146 that does 3ghz easy starts with a 1, my 3200+ that needs 1.7v to do 2.4ghz stable starts with a Z


edit: steve, what about that CACJE?

[ex2cib]

i just emailed AMD...i wonder if they will respond...hmmmm, guess it doesn't hurt to try

[high5]

what confuses me though, the E6 venice has a normal single core area, while i remember you showing a picture of the E6 san diego being a dual core with a single core enabled

well Venice is DH-E6 and that 'San Diego' should be JH-E6 AFAIK.

you need to check the full revision code.

[s7e9h3n]

hmmm.. the third line eh? i guess that would explain why there are variations between weeks with the same stepping.. perhaps lower 1st number/letter in the 3rd line is better.. my 146 that does 3ghz easy starts with a 1, my 3200+ that needs 1.7v to do 2.4ghz stable starts with a Z


edit: steve, what about that CACJE?

I think it's an opty 146

@ ex2cib: Good luck getting info If this info is available by just sending an e-mail, I think I'm gonna jump off a bridge.....