Personal though about the whole UTT stuff ...

[MeltedDuron]

apparantly there's a person sellin generic 1gb kits of new bh-5 on ebay for £75, i might offer to review one some day...

[wtz54321]

I need to emphasis once again ... I don't think it's what kind of UTT cause the
problem ... It's the UTT itself casue the problem ... Maybe the design of BH5 can
handle higher voltage which makes the possible faulty in the future chip last longer ,
but they may still die after some time period ... A very important thing is the burn in
process using high voltage + high temp to " ACCELERATE " the burn in time duration ...
But the acceleration factor will depend on the design of the chip , faulty UTT CH5 may
have a very big acceleration factor compare to faulty UTT BH5 ... But finally they will
still die as time goes by ...

[esdee]

Just a reminder, BH5 is .175nm process and they can handle 3.6-3.8V pretty nice
UTT "CH-5" is 0.13nm process and we still throw them 3.6-3.8V as if they where BH5

What would happen if we used 2.0-2.1V on Venice-Winchester? Barton and Tbreds could take it nicely.

peeps forget that mems are like CPUs, smaller proc--> less volt tolerance...even if they are Winbond chips

I Think it's an overkill for CH5 more than 3.5-3.6V (especially for 24/7 use) , they have smaller process than BH5

[wtz54321]

Just a reminder, BH5 is .175nm process and they can handle 3.6-3.8V pretty nice
UTT "CH-5" is 0.13nm process and we still throw them 3.6-3.8V as if they where BH5

What would happen if we used 2.0-2.1V on Venice-Winchester? Barton and Tbreds could take it nicely.

peeps forget that mems are like CPUs, smaller proc--> less volt tolerance...even if they are Winbond chips

I Think it's an overkill for CH5 more than 3.5-3.6V (especially for 24/7 use) , they have smaller process than BH5

Lots of UTT-CH die only at 3.2V ...

[esdee]

Lots of UTT-CH die only at 3.2V ...

there is that DFI issue too... maybe we should search for people that killed their UTT on non DFI too

[EMC2]

Thanks for the correction about the temperature and working current

But I did not get it about what you talk about the burn-in process ...

If the burin-in device failure rate is 0.5% , non-burn-in device failure rate is 1% , but it's chip level ... It's possible that 8% difference will be presented in module level ...

Could you explain more about what you thought of the burn in failure rate ?

You're welcome

You're assumption regarding the failure rate is slightly flawed... IF the individual chips were subjected to a burn-in process that reduced the infant mortality failure rate to 0.5% and there was no burn-in/testing done at the module level, then your assessment would be correct.

However, if the burn-in/testing is done at the module level then the "in field" infant mortality rate can be reduced to any fraction of a percent that one wishes by adjusting the acceleration factors.

I found the industrial information about the burn in condition of memory chip ... Apparently it's not possible for module maker to do some testing like this ...

Nope, the only things that can not be done after the memory die are packaged deal with visual inspection processes - for example examination of the die cuts and sampling of the physical structures.

ALL testing can be accomplished at the packaged part level and/or module level...

125 degree celcius is not possible for module level to do such kind of testing ...

It is possible. It only requires an understanding of the thermal characteristics of the package and module

System level stress screening is a very common practice in todays COTs arena... and is capable of providing sub 0.1% field failure rates when properly done.

Note: None of this is a statement regarding what the memory manufacturers are actually doing in regards to testing... only about what can be done.

[ramonlillo]

Just a reminder, BH5 is .175nm process and they can handle 3.6-3.8V pretty nice
UTT "CH-5" is 0.13nm process and we still throw them 3.6-3.8V as if they where BH5

What would happen if we used 2.0-2.1V on Venice-Winchester? Barton and Tbreds could take it nicely.

peeps forget that mems are like CPUs, smaller proc--> less volt tolerance...even if they are Winbond chips

I Think it's an overkill for CH5 more than 3.5-3.6V (especially for 24/7 use) , they have smaller process than BH5

I'm sorry but I don't think that volt tolerance is the point.

I've two sticks of 512Mb Twinmos Speed Premium UTT AA4T/44D.

As I wrote in another 3d, if I run them upon my old DFI Lanpary NF2Ultra RevB @22225/T1/240Mhz/3.2v, these sticks are simply COLD. Even with 250Mhz/3.5v (mobo has VDimm mod) the chips are only a little lukewarm.

But...if I run them upon my new DFI Lanparty NF4Ultra-D @22225/T1/240Mhz/3.2v (3.3v rail, not 5v: JP17@default!), the chips become incredibly HOT. Yes, I can't touch them!
I've also tryed @22225/T1, 200Mhz/3.2v and the situation is the same: chips are very very hot!

It' clear that this is not a voltage issue. The heat-power consumption is very different between my old DFI NF2 and my new DFI NF4, while the applyed voltage is the same. Than, I think that the "problem" is related to amperage: is it too much high?

[TMM]

Thats a fair point....

i'll be doing a Vdimm = Vio mod on my Neo2 soon with this UTT BH-5 and i'll see how hot they get will full amperage off the 3.3v line . Right now they barely get warm @ 2.8v, 2-2-2-5 208mhz.

[TMM]

hmm.. well i did the mod. Now they are running on 3.2v (my PSU 3.3v line = 3.2v ), and they get warmish. not "too hot to touch" but pretty warm. If i had to put a number on it i'd say 45-50*c. They only have the back flow from my XP-120 which has a 68cfm fan, so its not alot.
edit: hmm wtf, after a bit of burning in @ 3.2v they are cooler to touch - maybe 40-45*c now

Still seems that people that have DFI nf4 boards are running into heat problems - maybe its something to do with the difference in amperage of the 3.3v line vs 5v line? Most PSUs have more amps on the 5v compared to 3.3v

[gbomb944]

Probably why they're hotter in the nf4 is that they're running in dual channel and producing twice as much bandwidth at least. In case you don't believe me run a everest or sandra bandwidth test and see for yourself. Dual channel should access the memory at least twice as often. I'm not a super architecture expert but this is obvious.