Unlocked Venice 3000+

[Gogar]

would this help?
http://www.jasco-help.com/products/prod_rem.htm

I'd be careful using that close to the core though. IIRC the core is glued to the chip with epoxy as well.

[Mr. Tinker]

would this help?
http://www.jasco-help.com/products/prod_rem.htm

I'd be careful using that close to the core though. IIRC the core is glued to the chip with epoxy as well.

Maybe a bit of that stuff on a q-tip, lightly and take a lot of time.

The public A64 materials docs just say "epoxy." They also say BT Resin:

ADDITIONAL INFORMATION / ADDITIONAL MATERIALS
The following materials are not listed in EIA’s Material Declaration Template, but are contained in this package.
Material Wt% ppm mg
Aluminum < 0.39 < 3,900 < 155
Barium Titanate < 0.27 < 2,700 < 108
BT Resin < 2.6 < 26,000 < 1,036
Epoxy < 0.87 < 8,700 < 347
Iron < 0.087 < 870 < 35
Phosphorus < 0.0019 < 19 < 0.76
Silicon < 0.85 < 8,500 < 339
Silicone elastomer < 0.34 < 3,400 < 136
SiO2 Filler < 0.30 < 3,000 < 120
SiO2 glass mesh < 3.2 < 32,000 < 1,275
Tin < 0.14 < 1,400 < 56
Zinc < 0.0038 < 38 < 1.5
Zinc oxide < 0.14 < 1,400 < 56

Also, on page 375 of the "BIOS and Kernel Developer’s Guide for the AMD Athlon™ 64 and AMD Opteron™ Processors" it says this:

"New FID (NewFID)—Bits 5–0. This field is the new FID to transition to. If an attempt is made to write a NewFID value greater than MaxFID in the FIDVID_STATUS register then the MaxFID value is written instead. See Table 80 for FID code translations."

So we want to hide the maxFID value, or change it. I'm sure I'm not saying anything that hasn't been said.

[XFxGeforced]

on my s754 setup came some AS5 accidentally, I could buy a s939 setup... it died


on topic:

As I earlier said I got a s939 +300. venice.
first it's a crap overclocker (stuck at 2700mhz)
second: locked multi

xyus

hahaha, if 2.7 sucks then just give it to me, ill trade you my 2400+m 35w

[|SiLA|]

i just removed my ihs from me venice 3000 2,8 RS but 2,7 Daily my vitesta 566 can't go 310 1:1 but can handle 300 1:1 1T










and gain'd 5/6°C and 3 on the chipset

[Rabidmoose171]

omg its just laying on the bed... i hope it didnt get shocked... or maybe it got shocked and becomes unlocked.

[|SiLA|]

i've done it because i've red this thread..but no gain on multiplier..but atleast now i'm ready when someone will find out how to unlock it

[wittekakker]

unscharp pictures, i think your camera is to close. increase distance between camera and object and use a magnifying glas to zoom into the details of the proc. if you have a magnifying glass offcourse...

[sturmovik]

The pictures are not clear, and in such a unique case, we would need very detailed pictures. Try to use another digital camera and try to set the focus better this time.

[njkid32]

Here are my 3 chips my Venice, San Diego and my 3800 X2. I hope these help!

[largon]

There's something very solid white paste under the two black strips under the HS. And under the white strip - absolutely nothing.

The smaller black slab removed with a (sharp) surgical 10-blade:

[$ilver]

go deeper

[largon]

Nothing under the bigger one either...

This slaughtered 3000+ has a text "J9" in one of the corners. I'm just guessing but could it be that the package the core is glued to specifies the multi(es) that it can use?

J9 = FID ≤ 9?


What does a 3200+, 3500+ or FX's read?

[Mr. Tinker]

well, poop.

[sturmovik]

Maybe this should be called "plastic surgery"

[welshtom]

Nothing under the bigger one either...

This slaughtered 3000+ has a text "J9" in one of the corners. I'm just guessing but could it be that the package the core is glued to specifies the multi(es) that it can use?

J9 = FID ≤ 9?


What does a 3200+, 3500+ or FX's read?

Thats interesting, maybe pirs venice was glued to the wrong package?

Tom

We need to find out what other models have in that corner.

[FnF]

I can check what's on my winnie 3200+, but atm I don't want to remove the IHS of my Venice

[|SiLA|]

sorry guys i have no digital camera

it was made from my nokia 6600 only that's why so crappy

[largon]

I guess we want to see Pirs' CPU w/o HS. Or *any* other unlocked Venice.

|SiLA|'s / or anyone elses pics are quite useless if the proc on them isn't Pirs'...

If anyone is wondering, the proc I sliced 'n diced - is still alive.

[prueg]

Interesting thought... what multiplier was your Sandy running at? Would the bios then attempt to run your cpu with this multiplier after you swapped cpus over? And was this enough to change the cpu?

ie. Was the mobo's bios forceful in telling the cpu what multiplier to run at, and the cpu chucked a hissy-fit and started carrying on like "fine, from now on, YOU can tell me what multiplier to use... Im sick of doing all the thinking for myself!! How do you like that, Mr. ImAFussyBiosWhoHasToHaveMultipliersHisOwnWay?"

Or something like that.

[largon]

prueg,
AMD's tech docs describe how a multiplier is applied. Board, bios or previous proc can't affect that. The process is totally internal to the cpu.

But, if Pirs' core is glued to a package meant for FX, it would seem to explain why the multis are enabled.
There are some reports of partially unlocked multipliers (2 different 3000+ with multis up to 11). These 2 could have package of a 3500+.

Why would cores end up being glued to wrong packages is anyone's guess.

[Thorry]

Guys go measure resistance on the pins, that's the only way.

Everything done with the mulipliers is done inside the core.

[uwackme]

Yes Mr Tinker, exactly.

Based on Largon's picture nothing "obvious" seems to be there. I'd need to take a very close look at a dead Venice to try and ferret out the bridges. You'd need to also use a powerful light from underneath, as the bridge could be on an inner layer that the laser reached into.... an infrared laser could work without actually pocking a hole in the upper surface of the substrate.

So a light table to backlight the PCB/substrate material may show something on inner layers in the black covered areas.

Or they could be total dicks and put the bridges UNDER some of the resistor/capacitor SMD packs, and we need to remove all the caps/res's packs to figure out which the bridges are hidden under. Not a biggie but 1st time should be a DEAD Venice

But again, the chips are placed on the substrate BEFORE powerup-and-testing and are then speed binned. They cant possibly test the raw cores as the current requirements are so high no test fixture could handle the needs on a raw core level. So first the cores go on the substrate, then they speed-grade/test them, then they set the MAX-fid value somehow. It's always possible they put a PROM like circuit inside the core that gets "blown" once the chip is tested.... but that would be going overboard.

Nice pic's Largon, wish I could get my camera's macro down that fine!!

[FnF]

Well, On my Winnie there wasn't a J9, so prolly this will be only on Venice's... But Pirs, can't you take some pictures of it?

[|SiLA|]

Well, On my Winnie there wasn't a J9, so prolly this will be only on Venice's... But Pirs, can't you take some pictures of it?

he's not gonna remove the IHS tho'

but lucky him with that cpu

[Pirs]

Well, On my Winnie there wasn't a J9, so prolly this will be only on Venice's... But Pirs, can't you take some pictures of it?

http://www.pirs.vyrobce.cz/Images/venice/predek.jpg
http://www.pirs.vyrobce.cz/Images/venice/zadek.jpg