NF3/NF4 & TCCD - Highest stable clocks - REPORT IN !!!

[THunDA]

There is a Oc database at DFI street.. This is my recent entry so I figured to post it here also.. Its not a very high mem oc.. but I think its a good clock for 4x512mb's..



short description:
264x11 @ 2904Mhz, 1.325v + 126%
4x512mb's @ 2.5-4-8-3 @ 2.9v vdimm


Genie BIOS Settings:

FSB Bus Frequency - 264
LDT/FSB Frequency Ration - Auto
CPU/FSB Frequency Ratio - 11
PCI eXpress Frequency - 100Mhz

CPU VID StartUp Value - 1.55v

CPU VID Control - 1.325v
CPU VID Special Control - Avove VID * 126%
LDT Voltage Control - 1.20v
Chip Set Voltage Control - 1.60v
DRAM Voltage Control - 2.90v

DRAM Configuration Settings:

DRAM Frequency Set - 200 (DRAM/FSB:1/01)
Command Per Clock (CPC) - Disable
CAS Latency Control (Tcl) - 2.5
RAS# to CAS# delay (Trcd) - 04 Bus Clocks
Min RAS# active time (Tras) - 08 Bus Clocks
Row precharge time (Trp) - 03 Bus Clocks
Row Cycle time (Trc) - 09 Bus Clocks
Row refresh cyc time (Trfc) - 16 Bus Clocks
Row to Row delay (Trrd) - 02 Bus Clocks
Write recovery time (Twr) - 02 Bus Clocks
Write to Read delay (Twtr) - 01 Bus Clocks
Read to Write delay (Trwt) - 02 Bus Clocks
Refresh Period (Tref) - 3120 Cycles
Write CAS Latency (Twcl) - Auto
DRAM Bank Interleave - Enabled



DQS Skew Control - Auto
DQS Skew Value - 0
DRAM Drive Strength - Level 7
DRAM Data Drive Strength - Level 2
Max Async Latency - 8
DRAM Response Time - Fast
Read Preamble Time - 5.5
IdleCycle Limit - 256 Cycles
Dynamic Counter - Disable
R/W Queue Bypass - 16 x
Bypass Max - 07 x
32 Byte Granularity - Disable(8 Bursts)



==========


Prime95 + 3dMark2001SE + 2x CPU-Z + MBM + A64Tweaker + RivaTuner vid clocks :




3dMark2003 + Everest + SuperPi 32m + MBM :




3dMark2005 :




Aquamark 3d:




==========

EDIT..
btw.. some of the images are cropped just because thats the way it needs to be in the database ..