Here's a little info from the CPU side of the Tref picture...
Tref is controlled by 5 bits in one of the memory configuration registers of the A64. There are 4 "stock" refresh values, 1.95uS, 3.9us, 7.8us, and 15.6us. There are 8 MemClock frequency settings (based on a 200Mhz FSB) ranging from 100Mhz to 200mhz (you can see this in the divider ratios of the DFI BIOS).
What you get is a table that looks like that shown below, with values that don't correlate to the Tref settings in the BIOS... other than there are 4 groups of 8
Peace
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