OK, I have some questions...

1) Am I right in thinking that DQS alters where each data bit is sampled? So by changing its value we can get it to sample at the most stable part of the data bits... where they are most likely to have stabilised at either 1 or 0?

2) If what I said above is right, I guess selecting Increase & Value would mean the sampling is done "later" in each bit... so some kind of a delay is implemented in the AMD Memcontroller? Am I close?

3) So... If I AM on the right track I understand how we can "Increase" DQS, but what I don't get is how we can "Decrease" it?
Are the options "Increase"/"Decrease" relative to the MIDDLE of each data bit?
EG, the BIOS auto calculates the middle of each data bit based on the frequency, and tries to allocate a DQS value that will fall there... then if we select "Decrease" the value (I'm guessing a Timer/Counter preload value or something similar) will be reduced... moving the sampling closer to the previous clock edge?

If I am rambling please give me a virtual beeetch slap hehehe