UPDATE:- FSB_SENSE Bridges/Pins

[candjac]

From Inquirer article #6870 re oc.com.tw article re Barton 2500. "The chip is definitely a Barton clocked at 1833 Mhz (166x11.0). 1.65 V core and 90 deg. C core."...and...

"The L12 bridges control the bus speed."

This tends to confirm our circumstantial evidence about this FSB_SENSE signalling function on Tbreds, since the Barton and Tbred bridge layouts sem to be the same.

For final confirmation we still need a volunteer to make a continuity check from the 1st and 3rd L12 bridges to the 2 FSB_SENSE pins...all details/pics/pinouts etc well documented at
http://www.beachlink.com/candjac/index.htm FSB_SENSE article.
John C.

Edit:- There may be a way to verify whether mobos are incorporating this code/info, search bios settings for a FSB setting option that might have an "AUTO" option. This would suggest a signals source from the "system"...ergo the FSB_SENSE pins on the CPU??