Quote Originally Posted by Hans de Vries View Post
Well,

The latency results for simple sequental access show that prefetching is disabled in this ES....

In Sandy Bridge preftching reduces the L3 latency by a factor 2 or so. Latency reduction
is responsible for most of Sandy Bridge's IPC increase over Nehalem.

Regards, Hans
So pretty much what JF-AMD was saying. A lot of the ES chips have features disabled on purpose.