Quote Originally Posted by JF-AMD View Post
Each interlagos processor can run either 8 256-bit executions per cycle or 16 128-bit executions per cycle.

In newer AVX-updated code, we will have the same number or executions as Intel. In older non-AVX code we will have 16 128-bit executions to their 8 128-bit executions.
When speaking of Interlagos compared to Intel, it seems a bit silly to assume they won't avail themselves of the same trade-off that Interlagos uses to put up big throughput numbers, should they find its market compelling: taking advantage of the fact that power is non-linear with frequency, particularly at the top end. So you can drop the clock ~30%, and double the number of cores while remaining at the same power.

Intel can produce a 12- or 16-cored low-voltage/low-power Sandy Bridge, either directly, or with the yield- and cost-effective two-die MCM approach, and thereby take advantage of this same, almost completely design-agnostic principle.

So I think more focus on the non-MCM, baseline Zambezi/Valencia capabilities would be more likely to both illuminate the strengths and weaknesses of BD's *design* as well as let us properly gauge its true competitive position vs Intel's offerings.

(I'll grant you that as Magny is also an MCM/(low-speed/double-core), Interlagos vs Magny changes do result from BD design features.)