Quote Originally Posted by justapost View Post
The latest BKDG has some info about the C3 stepping. The chips will have two p-states for the nb and there will be a new C-state with the following characteristics. The L1/L2 caches will be flused to L3 or memory the cores will be in C1E state and running at ALTVID. Also there will be support for low voltage (1.35V) DDR3 1066.

http://support.amd.com/de/Processor_TechDocs/31116.pdf

p32 for the features
p48 2.4.2.2 NB p-states
p64 2.4.4.3 C5
That sounds interesting ...
This mean that finally NB will save the power as well. P-State 1 must be half the freq. of P-State 0 but any set vNB. This is good improvement.
Also they mention registers responsible for NB multis, but it is too early in the morning for me to figure out if reboot is still required to apply changes.