Intel is looking for a LRB3 uArch - RTL Engineer in Santa Clara, CA
Company: Intel
JobID: 563020 - LRB3 uArch - RTL Engineer
Category: Hardware & Electronics Design/Engineering - Junior (Mid-level, Experienced)
Location: Santa Clara, CA
Description
Position: LRB3 uArch - RTL Engineer
Responsibilities and Details
Description
As a member of the micro-architecture team in Intel's Enterprise Microprocessor Group (EMG), you will be responsible for defining and implementing portions of processors for graphics computing applications. Designs typically target high frequencies in a power-constrained, schedule-driven and product cost-conscious environment. Your responsibilities could lie in a processor's execution core, caches, system interface and would included proposing innovative solutions to micro-architecture design challenges, specifying or codeveloping performance models, specifying or running performance simulations, drawing actionable conclusions from the simulation results, cooperating with circuit designers to complete physical feasibility studies, authoring micro-architecture design specifications, developing high-level or Register-Transfer-Level (RTL) modeling methodology, coding high-level or RTL models, authoring validation plans, contributing to functional and performance validation, supporting physical design (e.g. to meet timing goals), participating in silicon debug and possibly leading a small team of engineers through any of the above. You will work in a team-oriented environment and would have to interact with engineers from other design disciplines and other groups.
Qualifications
You should possess a relevant educational qualification.
Additional qualifications include:
- Strong understanding of advanced computer architecture and micro-architecture design concepts spanning both core and system interconnect design
- Some processor design or chipset design experience would be an added advantage
- Knowledge and background in graphics hardware design, high speed industry standard I/O design and a working knowledge of physical design (for example, typical implementation styles, wire delay constraints) would be an added advantage
Job Category Engineering
Location USA-California, Santa Clara
Full/Part Time Full Time
Job Type Recent College Graduate
Regular/Temporary Regular
Reply With Quote
Bookmarks