How to set up GTL Ref Values for 45nm & 65nm

[mikeyakame]

Can someone explain with the GTL refs for the cores (.63 and .67 were are stock on P5Q) are different when its stated GTLref is .67 of FSB?

It's because with 45nm chips they use a lower Vtt of 1.10v as default, same goes with P45 NB it uses a lower default voltage than the older X48/X38/P35 chipsets.

The GTL0/3 and GTL1/2 aren't cores, they are mid/end GTL reference pins.

0/3 are data bus pins. 1/2 are address bus pins. They are logic sampling voltages, taken mid swing and end swing.

0/3 are kept down to 0.63x since data strobes aren't affected by signal ringing, and lower they are, the earlier swing logic can be determined and data transferred across the bus. It's to keep the low logic swing from overshooting too high before its stabilized, and high swing from undershooting too low before its stabilized. More accurate the receiver is at logic swing pickup, the less likely for inverse data strobe to be read as non-inverse data strobe, and the other way around.

Personally I think Intel optimized the P45 for the lower data bus GTL for the CPU to maximize the much cheaper parts performance. Nothing more nothing less. Lower voltages on NB and CPU require more expensive circuitry to accurately calculate swings and slews. Less room for error, and with P45 being what it was I don't think there was any other way as they couldn't make it more expensive.