i've heard a rumor flying around, that the new Packaging P4 2.4c SL6Z3s are actually disabled P4 EE chips. meaning , there are physically P4 EE chips with disabled 2mb L3 cache! from what i've been understanding, can someone pls verify if this is true!!


old P4 stepping vs new P4 2.4c stepping.http://www.xbitlabs.com/news/cpu/dis...031135052.html


notice the similarities with P4 EE pictured here.http://www.xbitlabs.com/articles/cpu...64-fx51_7.html