Quote Originally Posted by EnJoY View Post
... while memtesting 10 passed test#5 to see where your limit is.
what is this saying? run memtest test#5 with 10 successful passes? so, don't worry about running the other tests while trying to lower subtimings?

Quote Originally Posted by EnJoY View Post
It's just how memset reads the timings from the MCH register. It's not a bug in either memset, or the bios, it's simply how the register outputs the timing data.
ah ok. your screenshots from page 1 seem to show it correctly. Is this because we're using different mobos with different MCH registers?

Thanks again... very helpful as always!!