Official DFI LanParty UT X38-T2R(and LT) Discussion/Review/Overclock/Guide Thread

[eva2000]

Again clock fine delay and controller fine delay tweaking allowed me to stabilize my 2x 1GB Crucial Ballistix PC2-8500 @585Mhz 4-4-4-5 PL 5 at 2.51v.

• 540mhz 4-4-4-5 at 2.23v = okay
• 550mhz 4-4-4-5 at 2.31v = okay
• 565mhz 4-4-4-5 at 2.38v = okay
• 575mhz 4-4-4-5 at 2.45v = okay
• 580mhz 4-4-4-5 at 2.47v = okay
• 585mhz 4-4-4-5 at 2.49v = 4 errors in 1st pass of test #5 memtest86+ v1.70 loop
• 585mhz 4-4-4-5 at 2.51v = okay (manually set clock fine delay from current 3 to 4 and control fine delay for DIMM 1 + 3 changed from current 10 to manually set 11)

Single 32M


Dual 32M






DFI LP LT X38-T2R Bios Settings

PC Health Status
Adjust CPU Temp: +7C

CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 9x
- Target CPU Clock: 3512
CPU Clock: 390
Boot Up Clock: AUTO
DRAM Speed: 266/800
- Target DRAM Speed: 1172
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.2875
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.51
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.555
CPU VTT Voltage: 1.377
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: FAST
- Enhance Addressing: FAST
- T2 Dispatch: Enabled

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Aggressive
- DIMM 1 Clock fine delay: 4 (manually increased from 3)
- DIMM 2 Clock fine delay: 6 (manually set from current 6)
- Ch 1 Command fine delay: 11 (manually increased from current 10)
- Ch 1 Control fine delay: 7 (manually set from current 7)


Ch2 Clock Crossing Setting: More Aggressive
- DIMM 3 Clock fine delay: 4 (manually increased from 3)
- DIMM 4 Clock fine delay: 6 (manually set from current 6)
- Ch 2 Command fine delay: 11 (manually increased from current 10)
- Ch 2 Control fine delay: 5 (manually set from current 5)

Ch1Ch2 CommonClock Setting: More Aggressive

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 5
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance LVL (Read Delay) (tRD): 5

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Auto
- Channel 1 Phase 1 Pull-In: Auto
- Channel 1 Phase 2 Pull-In: Auto
- Channel 1 Phase 3 Pull-In: Auto
- Channel 1 Phase 4 Pull-In: Auto

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 14
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 4
Ranks Read to Read (tRDRD): 5
Ranks Write to Read (tWRRD): 4
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: 4