Seems that NV tried to use the chip to handle PCIe Gen2. it is weird that they do not build in the feature in the chipset.
according to "someone" the chip can handle the data traffic like this:
Upstream： PCI Express 16x
Downstream：2x PCI Express 16x, or 4x PCI Express 8x ，or 1x PCI Express 16x + 2x PCI Express 8x


here is teh original post[in Chinese]: http://news.expreview.com/2007-09-27...4591d3775.html