UPDATE:- FSB_SENSE Bridges/Pins

[candjac]

From Inquirer article #6870 re oc.com.tw article re Barton 2500. "The chip is definitely a Barton clocked at 1833 Mhz (166x11.0). 1.65 V core and 90 deg. C core."...and...

"The L12 bridges control the bus speed."

This tends to confirm our circumstantial evidence about this FSB_SENSE signalling function on Tbreds, since the Barton and Tbred bridge layouts sem to be the same.

For final confirmation we still need a volunteer to make a continuity check from the 1st and 3rd L12 bridges to the 2 FSB_SENSE pins...all details/pics/pinouts etc well documented at
http://www.beachlink.com/candjac/index.htm FSB_SENSE article.
John C.

Edit:- There may be a way to verify whether mobos are incorporating this code/info, search bios settings for a FSB setting option that might have an "AUTO" option. This would suggest a signals source from the "system"...ergo the FSB_SENSE pins on the CPU??

[candjac]

Bump

[DaGooch]

On the Epox 8RDA+ there is a jumper for 166. Therfore, manual on this board.

[scnspk]

candjac,

The L12 experiment with a tbred B 2200+ on an Epox 8K9A2 was posted here http://www.oc.com.tw/article/0212/re...le.asp?id=1154
and translated here http://www.flickerdown.com/phpBB2/viewtopic.php?t=2301
Apparently, the 2200+ tbred boots at 166fsb when fsb1 is reset low by closing the 2nd right L12. The multiplier was recognised as 5.5x since the CPU is also unlocked.

scnspk

[candjac]

Originally posted by scnspk
candjac,
The L12 experiment with a tbred B 2200+ on an Epox 8K9A2 was posted here http://www.oc.com.tw/article/0212/re...le.asp?id=1154 and translated here http://www.flickerdown.com/phpBB2/viewtopic.php?t=2301
Apparently, the 2200+ tbred boots at 166fsb when fsb1 is reset low by closing the 2nd right L12. The multiplier was recognised as 5.5x since the CPU is also unlocked.
scnspk

Thanks scnspk, but we were aware of that experiment and the translation. Also we had predicted at our site that the 1st and 3rd L12s would be involved, with the 3rd (2nd from right) being toggled open/closed to go between 133 and 166MHz. So their experiment with the fsb1 bit/ 3rd from left L12 was a welcome confirmation and not a surprise. But there are 2 other issues before we completely "close the loop".

1:- The translation wrote..."Also note the L12 bridges to the left of L5: On the L12 bridges, cutting the second bridge from the right (i.e. cutting that bridge and the rightmost bridge) enables a 133MHz FSB" End quote.

So they are saying that the 2 bits are controlled by the 3rd and 4th L12s from the left...whereas based on the Truth Table logic presented in 25175.pdf and pics of 133MHz and 166MHz CPUs, the 2 bits should only be able to be controlled by the 1st and 3rd L12s. Now this leaves agreement on the 3rd L12, the one that toggles between 133/166, but disagreement on fsb0 and its L12 bridge. We feel confident it's the 1st one from the left because it's the "only one possible" with the Truth Table logic/Code data as published. Anyone can check the logic at the FSB_SENSE article, link original post.

2:- We'd also like for someone to make continuity checks between the L12s and the fsb[1:0] pins AH30 and AG31 as another/final check. This would also put to rest the issue we raise in 1:- above about whether the other L12 is the 1st or the 4th from the left. Believe "Nohto" may be working on this. Thanks for the opportunity to try to clarify issues
John C.

[scnspk]

Also note the L12 bridges to the left of L5: On the L12 bridges, cutting the second bridge from the right (i.e. cutting that bridge and the rightmost bridge) enables a 133MHz FSB, but the Barton¡¦s L12 bridges are intact except for the rightmost bridge.

candjac,

yes, the translated version did refer to an open rightmost L12 in Barton and Tbred. However, their picture showed the exact opposite, i.e., the only opened L12 is leftmost in Barton. I think there might be either a typo and/or translation error, so the 2 bits are likely controlled by the 1st and 3rd L12. scnspk