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Thread: AMD Phenom II X6 | Turbo CORE 101

  1. #76
    Xtreme Enthusiast TJ TRICHEESE's Avatar
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    surely if an application only uses three cores and three throttle up there is only a 1 in 2 chance of the program using the overclocked cores, or does the CPU throttle up the 3 cores with the highest usage

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    Quote Originally Posted by TRICHEESE View Post
    surely if an application only uses three cores and three throttle up there is only a 1 in 2 chance of the program using the overclocked cores, or does the CPU throttle up the 3 cores with the highest usage


    Sometimes it amazes me how ppl think they are so clever they know something that those who as a work desing cpu:s wont.

    It would be fine to have it like this:

    "How does the cpu know to boost most utilized cores all the time"

  3. #78
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    yes, but im meaning diferent system lock cores. We will see
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    Quote Originally Posted by TRICHEESE View Post
    surely if an application only uses three cores and three throttle up there is only a 1 in 2 chance of the program using the overclocked cores, or does the CPU throttle up the 3 cores with the highest usage
    Read the thread again,it's been explained before. There is dedicated HW in Thubans that dynamically clocks used cores to 3.6Ghz (for 1090T model) and these clock changes are extremely fast so the thread bouncing that happens in Vista/7 OS won't be an issue since the boosted cores can be random(the ones that are used in any moment of time if the condition for the Turbo Core is met: CPU utilization is less or equal to 50%).

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    Quote Originally Posted by TRICHEESE View Post
    surely if an application only uses three cores and three throttle up there is only a 1 in 2 chance of the program using the overclocked cores, or does the CPU throttle up the 3 cores with the highest usage
    Turbo CORE rapidly adjust which 3 cores are in Turbo. Realy fast.

    If an application has multiple, demanding simultaneous threads then it is likely to benefit from all six true cores. If these threads are intermittent or if there are few threads, Turbo CORE is ready.

    Turbo CORE is designed not to harm performance on highly threaded loads. Do not think of three cores being put to idle; the OS places the cores in a low P-state and Turbo CORE smartly accelerates the remaining cores. Turbo CORE is opportunistic.
    Last edited by 64NOMIS; 04-10-2010 at 06:22 AM.

  6. #81
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    AMD Phenom II X6 1055T Processor Hits Retail in China
    http://en.expreview.com/2010/04/10/a...hina/7035.html

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    Quote Originally Posted by onethreehill View Post
    AMD Phenom II X6 1055T Processor Hits Retail in China
    http://en.expreview.com/2010/04/10/a...hina/7035.html
    According to OPN it will be a new stepping. Probably "E".
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    Thuban is revE

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    This is definitely going to be in my next ground up build for my Eyefinity build! Awesome.
    BTW Informal, do you have any idea what CORE stands for? I guess its an acronym for something?
    As per Simons post, maybe the O stands for opportunistic and the C for core. E for execution?
    Last edited by flippin_waffles; 04-10-2010 at 07:52 AM.

  10. #85
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    Quote Originally Posted by flippin_waffles View Post
    This is definitely going to be in my next ground up build for my Eyefinity build! Awesome.
    BTW Informal, do you have any idea what CORE stands for? I guess its an acronym for something?
    As per Simons post, maybe the O stands for opportunistic and the C for core. E for execution?
    you forgot R which stands for Rapid

    Turbo Core Opportunistic Rapid Execution...lol
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    Quote Originally Posted by Oliverda View Post
    Sounds good but what is "RC-wire"?
    There is no such thing as an 'RC-wire', Hans means RC wire delay. Chips are wired up by etching or depositing metal lines within a dielectric material that is electrically isolating. Wires themselves have an intrinsic resistance and, also run parallel or one above another, due to the proximity two separate conductors separated in space setup a capacitance.

    The result is a complicated RC circuit, where the capacitor/resistor have an intrinsic charge time. The effect is to delay propogation of signals through the matrix but some fundamental frequency or time delay. The time constant (tc) is proportional to the capacitance and resistance of that arrangement. tc=R*C (R=resistance and C = capacitance). The concept of RC delay in an RC circuit is taught in most freshman level physics courses when they study electricity and magnitism.

    The industry must work to minimize this effect because a) it causes latency in signal propogation, b) works to limit clock speed, and c) increases power dissipation. This is why there was a move to copper lines 8-10 years ago, and this is why you hear all the hubbub about low-k and ultra-low k material (not to be confused with high-K for gates). To decrease the time constant you want low R and low C, copper has lower R per unit length than does aluminum (which was used prior to copper). Capacitance gets lower with lower k (dielectric constant) material.

    Jack
    Last edited by JumpingJack; 04-10-2010 at 05:00 PM.
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  12. #87
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    Quote Originally Posted by ridney View Post
    you forgot R which stands for Rapid

    Turbo Core Opportunistic Rapid Execution...lol
    Heh yeah I couldn't come up with something good for R, but Rapid is good, I like!

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    Quote Originally Posted by JumpingJack View Post
    There is no such thing as an 'RC-wire', Hans means RC wire delay. Chips are wired up by etching or depositing metal lines within a dielectric material that is electrically isolating. Wires themselves have an intrinsic resistance and, also run parallel or one above another, due to the proximity two separate conductors separated in space setup a capacitance.

    The result is a complicated RC circuit, where the capacitor/resistor have an intrinsic charge time. The effect is to delay propegation of signals through the matrix but some fundamental frequency or time delay. The time constant (tc) is proportional to the capacitance and resistance of that arrangement. tc=R*C (R=resistance and C = capacitance). The concept of RC delay in an RC circuit is taught in most freshman level physics courses when they study electricity and magnitism.

    The industry must work to minimize this effect because a) it causes latency in signal propogation, b) works to limit clock speed, and c) increases power dissipation. This is why there was a move to copper lines 8-10 years ago, and this is why you hear all the hubbub about low-k and ultra-low k material (not to be confused with high-K for gates). To decrease the time constant you want low R and low C, copper has lower R per unit lenth than does aluminum (which was used prior ot copper). Capacitance gets lower with lower k (dielectric constant) material.

    Jack
    Really well explained in simple language
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    affordable hexacore .. interestingg

    any tips as to what motherboard (chipset) and memory i should combine it with ? For overclocking of course !
    I'm coming over from long time intel .. and those 2 worlds are very different nowadays i think .


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    You'll need AM2+/AM3 board that supports Thuban hexa core chips (BIOS level) and DDR2(in case of AM2+ board) or DDR3(in the case of AM3 board).
    Thuban goes both ways,AM2+ and AM3,since the integrated memory contr. inside the chip supports both DDR standards .

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    Quote Originally Posted by JumpingJack View Post
    There is no such thing as an 'RC-wire', Hans means RC wire delay. Chips are wired up by etching or depositing metal lines within a dielectric material that is electrically isolating. Wires themselves have an intrinsic resistance and, also run parallel or one above another, due to the proximity two separate conductors separated in space setup a capacitance.

    The result is a complicated RC circuit, where the capacitor/resistor have an intrinsic charge time. The effect is to delay propegation of signals through the matrix but some fundamental frequency or time delay. The time constant (tc) is proportional to the capacitance and resistance of that arrangement. tc=R*C (R=resistance and C = capacitance). The concept of RC delay in an RC circuit is taught in most freshman level physics courses when they study electricity and magnitism.

    The industry must work to minimize this effect because a) it causes latency in signal propogation, b) works to limit clock speed, and c) increases power dissipation. This is why there was a move to copper lines 8-10 years ago, and this is why you hear all the hubbub about low-k and ultra-low k material (not to be confused with high-K for gates). To decrease the time constant you want low R and low C, copper has lower R per unit lenth than does aluminum (which was used prior ot copper). Capacitance gets lower with lower k (dielectric constant) material.

    Jack




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    hmmmm when will AMD Desktop CPU has a multithread like Intel HT
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    Quote Originally Posted by PatRaceTin View Post
    hmmmm when will AMD Desktop CPU has a multithread like Intel HT
    A. never
    B. when Heck freezes over.
    C. see bulldozer for better options.
    lol jk

    programing still playing catch up.

    so hyper threading can't replace real cores, yet.
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    Quote Originally Posted by demonkevy666 View Post
    A. never
    B. when Heck freezes over.
    C. see bulldozer for better options.
    lol jk

    programing still playing catch up.

    so hyper threading can't replace real cores, yet.
    And it shouldn't. HyperThreading is only good for servers, in which more servers could be hosted with dedicated threads or crunching/folding, in which more threads could run more efficiently.

    If multi-threaded apps benifit from more threads without more cores there is something wrong with the CPU architecture or the programming.

    Like has been said before, it's a band-aid for pipelines which are too long. Core i7 is like the Pentium 4 of it's day.
    Smile

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    And also, real man use real cores xD.
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    These are being sold in china still no review??

    I mean no forum info, etc?
    Coming Soon

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    I'm curious that the 960T will be Black Edition or not...
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    Quote Originally Posted by flippin_waffles View Post
    This is definitely going to be in my next ground up build for my Eyefinity build! Awesome.
    BTW Informal, do you have any idea what CORE stands for? I guess its an acronym for something?
    As per Simons post, maybe the O stands for opportunistic and the C for core. E for execution?
    Sorry I missed your question before . It should be acronym but I have no info on what it could mean. I can ask around and see if I get any info on it . The launch is soon so we are going to know anything there is to know about Tubans soon enough

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    Quote Originally Posted by Oliverda View Post




    Btw I've found a strange identity.

    Opteron 170 vs X6 1055T


    hmm will these OC like opterons? xmas coming early? haha

    im sure memory will OC and be stable at stock speeds for alot more budget kits
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    This chip sounds pretty exciting to me with the Turbo features. I am going to have to check this CPU out and see what heat loads it has. Looks like a very nice chip

    It appears from those retail box shots that is has a stock heat sink like the ones that come with 965/955's, thats a good sign its not a really hot running chip. Compared to the new Gulftown Heat Sink.

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