Graphene Transistors @ 100 gigahertz

[verndewd]

pop quiz
whats the cut off speed of a silicon transistor?
A: theoritical max speed before cut off 40ghz.

what is the current transistor speed?
lets say current transistor speeds on CPU's are maxed

100ghz = 60% frequency boost in cpu speeds (theoretically)

a person needs to know the classification of transistors as in wether they are RF or not EG

Fastest Transistor Approaches Terahertz Speed
Peter Singer, Editor-in-Chief -- Semiconductor International, 1/1/2007


Scientists at the University of Illinois at Urbana-Champaign have again broken their own speed record for the world's fastest transistor. With a frequency of 845 GHz, their latest device is ~300 GHz faster than transistors built by other research groups, and approaches the goal of a terahertz device.

Made from indium phosphide and indium gallium arsenide, “The new transistor utilizes a pseudomorphic grading of the base and collector regions,” said Milton Feng, Holonyak Chair Professor of electrical and computer engineering at U of I. “The compositional grading of these components enhances the electron velocity, hence, reduces both current density and charging time.”

With this latest device, Feng and his research group have taken the transistor to a new range of high-speed operation, finally bringing the “Holy Grail” of a terahertz transistor within reach. In addition to using pseudomorphic material construction, the researchers also refined their fabrication process to produce tinier transistor components. For example, the transistor's base is only 12.5 nm.


Clocking in at 845 GHz, the transistor is fabricated with InP and GaAs, and employs pseudomorphic grading of the base and collector regions. (Source: University of Illinois)


“By scaling the device vertically, we have reduced the distance electrons have to travel, resulting in an increase in transistor speed,” said graduate student William Snodgrass, who described the new device at the International Electronics Device Meeting (IEDM) , held in San Francisco Dec. 11-13. “Because the size of the collector has also been reduced laterally, the transistor can charge and discharge faster.”

Operating at room temperature (25°C), transistor speed is 765 GHz. Chilled to -55°C, the speed increases to 845 GHz. Feng, Snodgrass and graduate student Walid Hafez (now at Intel Corp .) fabricated the high-speed device in the university's Micro and Nanotechnology Laboratory. In addition to further increasing the transistor speed, Feng wants to reduce the current density even more, which will reduce junction temperature and improve device reliability.

Find more information on wafer processing.

http://www.semiconductor.net/article...ertz_Speed.php

I have been following graphene for a couple years well around 3 to be exact , since the smallest transistor was made with graphene? memory fails me here, but I do believe that graphene research could in fact be something used on cpus, but as Jack can tell you there is a pile of compatibility factors with multi layered chips as well as through via solutions etc etc . We'll know what it can do when thet create some dram with it or a logic chip of any flavor.

Question is, in an 11 layer stack how many graphene layers and how will electron ballisticity be maximized out side the graphene. Very big puzzle here, and this is just one promising piece.

[verndewd]

unfortunately as clock speed increases IPC GOES DOWN, due to starvation [caches only can help so much] largely because memory latency is holding performance back. http://www.behardware.com/articles/6...-duo-test.html (a legacy read but important for this discussion)

In fact if you drop a 100Ghz version of any processor on the market into a current system, the performance increase would be less than 10%

Thats where I am anxiously waiting for optical mobo pathways and optical data through put on chip, of course there are issues like cost and wave devices to take it from light to electron, but Intel has done some great work in the field as well as others, its still taking so long to get past current materials trends to something that could even allow bus and mobo through put to operate at cpu core speeds, that would be a huge perf boost on current technology.

[JumpingJack]

pop quiz
....

Hey Vern -- great to see you active again.

Jack

[verndewd]

Hey Vern -- great to see you active again.

Jack

hey my friend hows the kid?

[JumpingJack]

hey my friend hows the kid?

Just had my second not long ago ... one was managable, but two chews up almost all my free time.

I wouldn't trade it for anything in the world. Worth every bit of the effort.

[nn_step]

Thats where I am anxiously waiting for optical mobo pathways and optical data through put on chip, of course there are issues like cost and wave devices to take it from light to electron, but Intel has done some great work in the field as well as others, its still taking so long to get past current materials trends to something that could even allow bus and mobo through put to operate at cpu core speeds, that would be a huge perf boost on current technology.

unfortunately Optical data pathways don't have lower latency [unless we start storing data as light rather than electricity]
Which would in many cases reduce performance, but in cases where bandwidth is King then yes you are correct they will have a benefit.

The one thing everyone forget is that the biggest problem with increasing performance is LATENCY, NOT bandwidth.
Bandwidth is easier to solve; if you want double the bandwidth, just double the number of memory channels.

[verndewd]

Just had my second not long ago ... one was managable, but two chews up almost all my free time.

I wouldn't trade it for anything in the world. Worth every bit of the effort.

nice, doing any preschool teaching?, I have seen some products out that can get a kid reading at the toddler stage. Congrats on the second and a ton of wishing you well in parenthood. Glad there will be more jacks coming into the world be they male or female leaving out the rip on society ere

[verndewd]

unfortunately Optical data pathways don't have lower latency [unless we start storing data as light rather than electricity]
Which would in many cases reduce performance, but in cases where bandwidth is King then yes you are correct they will have a benefit.

The one thing everyone forget is that the biggest problem with increasing performance is LATENCY, NOT bandwidth.
Bandwidth is easier to solve; if you want double the bandwidth, just double the number of memory channels.

actually , and youll have to pardon my forgetting the link but photonic data stuff is actually being done in labs. If i come across the link ill get it to you, it may not have been specific to stored data but it was definitely a close relative. sorry for the lack of linkage , i will look for it, no promises.

[saaya]

Thats where I am anxiously waiting for optical mobo pathways and optical data through put on chip, of course there are issues like cost and wave devices to take it from light to electron, but Intel has done some great work in the field as well as others, its still taking so long to get past current materials trends to something that could even allow bus and mobo through put to operate at cpu core speeds, that would be a huge perf boost on current technology.

are you sure?
i cant see how we are bandwidth limited in any way right now...
like nn_step said, what we need is latency improvements, and for that we need better dram, flash, and processors...

[nn_step]

are you sure?
i cant see how we are bandwidth limited in any way right now...
like nn_step said, what we need is latency improvements, and for that we need better dram, flash, and processors...

Actually the most promising technology I have seen in the past couple years was Z-RAM with 3ns response times.
and the Lightweight Profiling Specification by providing internal hardware monitor with runtimes, to observe information about executing process and help the re-design of software to be optimized.

The biggest areas where performance can be improved in a modern system are:
1) Getting data into the cache before it is needed [nearly impossible without software prefetch hints]
2) Improving the quality of the code already written. [Sometimes less is alot more]

[verndewd]

are you sure?
i cant see how we are bandwidth limited in any way right now...
like nn_step said, what we need is latency improvements, and for that we need better dram, flash, and processors...

This concept was mentioned in an article I wrote and linked to one of the foremost tech journals online. imagine if through put was all at core speeds, That can be done with optical pathways once cost and converters are appropriate. I even forget the site that mentioned the optical mobo thing back in 07. time to go link hunting i guess.

Hers one of the latest developments

http://physicsworld.com/cws/article/news/41674

Older stuff

http://spectrum.ieee.org/computing/h...ansistor-laser

That publication is the one that went into optical motherboard paths.

And some really really good side reading on graphene and such

http://www.mrs.org/s_mrs/sec.asp?CID=1920&DID=84063

[flutie98]

This concept was mentioned in an article I wrote and linked to one of the foremost tech journals online. imagine if through put was all at core speeds, That can be done with optical pathways once cost and converters are appropriate. I even forget the site that mentioned the optical mobo thing back in 07. time to go link hunting i guess.

Hers one of the latest developments

http://physicsworld.com/cws/article/news/41674

Older stuff

http://spectrum.ieee.org/computing/h...ansistor-laser

That publication is the one that went into optical motherboard paths.

And some really really good side reading on graphene and such

http://www.mrs.org/s_mrs/sec.asp?CID=1920&DID=84063

A better sight than just MRS for graphene research is www.graphenetimes.com

[saaya]

This concept was mentioned in an article I wrote and linked to one of the foremost tech journals online. imagine if through put was all at core speeds, That can be done with optical pathways once cost and converters are appropriate. I even forget the site that mentioned the optical mobo thing back in 07. time to go link hunting i guess.

Hers one of the latest developments

http://physicsworld.com/cws/article/news/41674

Older stuff

http://spectrum.ieee.org/computing/h...ansistor-laser

That publication is the one that went into optical motherboard paths.

And some really really good side reading on graphene and such

http://www.mrs.org/s_mrs/sec.asp?CID=1920&DID=84063

thx
i guess if the cpu, the system bus AND the interface connecting everything would run at the same speed latencies would drop... and that would help performance... but the performance boost would be a result of the reduced latency, not added bandwidth, and i dont think it would be all that much... every single benchmark and app out there shows that computers arent bandwidth limited... at all...
back in the fsb days that was the case, but ht and qpi? a limitation?

memory has a limited latency and throughput, so does every other components on a mainboard or in a pc... so if you connect it all with a super wide high bandwidth bus... its not going to change much if anything at all... youd need at least the interfaces to run at the same high speed as well, if not the whole chips... that just doesnt make sense, and i dont think its ever going to happen...

im surprised you think the system bus is a main limitation in system performance, when we have qpi and hyper transport which dont affect system performance whatsoever even if you reduce their bus bandwidth and speed, and thus latency, to a fraction of the stock speed...

[Chumbucket843]

unfortunately Optical data pathways don't have lower latency [unless we start storing data as light rather than electricity]
Which would in many cases reduce performance, but in cases where bandwidth is King then yes you are correct they will have a benefit.

The one thing everyone forget is that the biggest problem with increasing performance is LATENCY, NOT bandwidth.
Bandwidth is easier to solve; if you want double the bandwidth, just double the number of memory channels.

increasing memory channels increases latency and it is limited to 4-5 channels. the problem is that dram architecture is designed to favor density over bandwidth over latency. latency can be hidden through more threads (ie gpu's or hyperthreading) but the lack of BW can not be hidden. i find it ironic that today's random access memory is far better at sequential access.

[damha]

i find it ironic that today's random access memory is far better at sequential access.

Where did that come from? Sources please.

[verndewd]

http://www.dewassoc.com/performance/...ry_latency.htm

Output driving latency
Like the word line activation latency, this delay is basically caused by the RC of driving a long wire across the die. Again, circuit techniques may be used to reduce delay, as well as careful layout to reduce the length of the wire. Also, new packaging methods such as lead-on-chip can be used to reduce wire length.

pretty decent rundown on memory latencies. There have been some optical dram experiments but I dont think that means much to classical dram design as of yet. It was designed for networks but I think the point of optical tech is approaching validity to modern computation via several roundabout ideas. As stated in the article power could be increased as well as die size for much faster Ram, its simply not being done , likely for a plethora of reasons.

[Otis11]

Where did that come from? Sources please.

Unfortunately, I dont have a source, but I can back up Chumbucket on that one...

RAM is set up as a grid that can only be accessed one row at a time, but you can access as many locations on that row as you want, so many times programmers (I believe at the compiler level, but i could be mistaken) will play little tricks to get data that will be needed together in the same row.

I'd draw a diagram to help, but that would take a while on a computer, and unfortunately can't find an image that works well for this explanation...

[damha]

DRAM science is extremely complex. Generalizing it like this is easy and more than likely wrong. I know what I know, but without proof I can't speak either. We need someone in here who is into DRAM engineering to clear it up.

[Otis11]

DRAM science is extremely complex. Generalizing it like this is easy and more than likely wrong. I know what I know, but without proof I can't speak either. We need someone in here who is into DRAM engineering to clear it up.

Scratch that... (had something written, but decided to just explain it a bit more)

So DRAM has a decoder to chose which row exactly you want to access at then and the end of every column there is a mux to read in all the data passed to it from that column and using boolean logic from the 0s and 1s it decides what the value stored at that particular location was. Granted I'm leaving out a lot of details about what kind of transistors it is reading from, the 6 transistor and the 8 transistor approach and the cross over inverters that act as amplifiers, but I do not feel I'm being too general in my above conclusion.

But then again, I'm not a DRAM engineer...

So if anyone want's to correct me on any of that, I'd be more than happy to hear it!