Istanbul Demoed, Let's Drink Soda

[Macadamia]

http://www.techreport.com/articles.x/16448

HT assist seems to be something nifty. Plus HT3.0 will suffice for 12 cores and help 24 thread scaling.

For a drop-in upgrade to Socket F it seems wicked nice. It won't win SAP SD benchmarks because it's not quad-channel DDR3 at work yet, but for HPC and Virtualization it should definitely give some sense to a certain CPU called Gainestown.


(And no, Gulftown was not on demo at IDF. It should not catch Q3 or Q4 of 2009, probably Q2 2010 for servers. Magny probably comes 1 quarter later with QC DDR3.)

[hurleybird]

1MB L2 per core... typo?

[informal]

http://www.techreport.com/articles.x/16448

HT assist seems to be something nifty. Plus HT3.0 will suffice for 12 cores and help 24 thread scaling.

For a drop-in upgrade to Socket F it seems wicked nice. It won't win SAP SD benchmarks because it's not quad-channel DDR3 at work yet, but for HPC and Virtualization it should definitely give some sense to a certain CPU called Gainestown.


(And no, Gulftown was not on demo at IDF. It should not catch Q3 or Q4 of 2009, probably Q2 2010 for servers. Magny probably comes 1 quarter later with QC DDR3.)

Wicked demo,thanks for posting the news Macadamia .

24 cores in task manager

What is more interesting is the perf. scaling. 1.68x more performance in Stream benchmark for 1.5x more cores that all the chances are were working at lower clocks in Istanbul's case.
Probable reason: "HT Assist"

Part of the answer, it seems, may be a feature new to Istanbul that AMD calls HT assist (presumably for HyperTransport assist). This feature is what the company calls a probe filter (and may more commonly be called a snoop filter) that functions to reduce traffic on socket-to-socket HyperTransport links by storing an index of all caches and preventing unnecessary coherency synchronization requests. Current Opteron systems use a broadcast-based probe protocol, sending probe requests to all sockets. Istanbul, instead, either knows that no probes are required or is able to do a directed probe to a single socket. (Although it may still use broadcasts in certain, specific situations.) Istanbul's probe filter stores its data in the processor's L3 cache. The amount of cache space dedicated to probe filter storage, AMD says, will be configurable in the BIOS, and the more space dedicated to probe filter storage, the more granular its operation will be.

Comment on validation of six core parts:

Beyond that, AMD expects system vendors to treat Istanbul very much like any other new Opteron speed grade, with a much easier qualification path than an all-new product. That should mean fairly quick and widespread adoption of six-core Opterons among vendors shipping Shanghai-based systems today, if all goes as planned.

The Istanbul core obviously taped out some time ago,probably Q3 2008.Being souped-up and upgraded Shanghai,AMD should have no problems launching the parts in Q3.

[Chad Boga]

The Istanbul core obviously taped out some time ago,probably Q3 2008.Being souped-up and upgraded Shanghai,AMD should have no problems launching the parts in Q3.

Don't these sorts of products tend to show up 9 to 12 months after a demo like this?

[haylui]

hopefully AMD could roll out this chip to counter nehalem bsed xeon CPU

[informal]

Don't these sorts of products tend to show up 9 to 12 months after a demo like this?

Nope,12 months after the tape out(provided the health of the stepping/revision is good-which in case of Istanbul should be no problem due to the "nature" of the chip and it being based on already proven Shanghai core)

[Macadamia]

Don't these sorts of products tend to show up 9 to 12 months after a demo like this?

Timeline:

45nm Shanghai first demo (just working CPUs, I don't think even load testing was involved): March 2008

Shanghai availability: Oct-Nov 2008 (We'll say Nov for convenience's sake)

Istanbul first demo, with load tests: Late Feb 09

Istanbul availability: At worst Q4 09, BUT this time AMD doesn't need to deal with a pesky process transition. Still I'm putting availability at early Q4, which is same as Shanghai.

[Chad Boga]

Timeline:

45nm Shanghai first demo (just working CPUs, I don't think even load testing was involved): March 2008

Shanghai availability: Oct-Nov 2008 (We'll say Nov for convenience's sake)

Istanbul first demo, with load tests: Late Feb 09

Istanbul availability: At worst Q4 09, BUT this time AMD doesn't need to deal with a pesky process transition. Still I'm putting availability at early Q4, which is same as Shanghai.

Okay, I'm too lazy to look, but is Istanbul then likely to be out before the 8 core Nehalem variant?

[Macadamia]

Okay, I'm too lazy to look, but is Istanbul then likely to be out before the 8 core Nehalem variant?

Maybe. But they're not exactly going to be competition.

Nehalem EX is 4+ CPU Sockets, each likely starting to sell at $2.5k USD and above. AMDs chance of competing with it will be its MCM (Hypertransport, not FSB) Istanbul (Magny-Cours) products with quad channel buffered DDR3 support.

The MCM Istanbul is perhaps more interesting than Nehalem EX, mostly because it can be implemented in 2P configurations too, at the cheaper rate AMD is charging now (<1.5k USD). It's going against Gulftown at 2P configs.

[Shintai]

Istanbul have to beat Nehalem-EP first. Gulftown could potentially take Magny-Cours alone. Its a hotfix, not a solution to their lacking core performance parts. They need a new core design to solve the issue. And specially something like SMT in the serverspace.

[m^2]

Maybe. But they're not exactly going to be competition.

Nehalem EX is 4+ CPU Sockets, each likely starting to sell at $2.5k USD and above. AMDs chance of competing with it will be its MCM (Hypertransport, not FSB) Istanbul (Magny-Cours) products with quad channel buffered DDR3 support.

The MCM Istanbul is perhaps more interesting than Nehalem EX, mostly because it can be implemented in 2P configurations too, at the cheaper rate AMD is charging now (<1.5k USD). It's going against Gulftown at 2P configs.

They surely are a competition. Istanbul scales to 48 cores. Nehalem to 32 with 64 threads (some say that double as much). Fight!

[informal]

Istanbul have to beat Nehalem-EP first. Gulftown could potentially take Magny-Cours alone. Its a hotfix, not a solution to their lacking core performance parts. They need a new core design to solve the issue. And specially something like SMT in the serverspace.

SMT in nehalem costs a lot in terms of core logic die space ,it doesn't come free you know. One Nehalem core is 24.4mm2,one Shanghai core is 15.3mm2,a staggering 60% difference.So 6 Shanghai cores at the same clock as Nehalem would outperform it while taking up 91.8mm2 compared to 97.6mm2 for Nehalem design-so less total core logic die area for more perf. It's easy to see AMD opted for core count over SMT strategy with Shanghai.It's less expensive from R&D pov,easier to design and is easier to validate(you just add more already proven cores at the time your process matures).Downside with Istanbul is a need for additional L1/L2 caches but it should add only about ~9mm2 of additional space on the die(7.5mm2 per MB of sram in 45nm Shanghai design)

Nothing comes cheap,SMT is no exception.I expect that Bulldozer cores feature some form of SMT(or maybe even DSMT?),but until then Shanghai/Istanbul/M. Course will do just fine.

[Shintai]

SMT in nehalem costs a lot in terms of core logic die space ,it doesn't come free you know. One Nehalem core is 24.4mm2,one Shanghai core is 15.3mm2,a staggering 60% difference.So 6 Shanghai cores at the same clock as Nehalem would outperform it while taking up 91.8mm2 compared to 97.6mm2 for Nehalem design-so less total core logic die area for more perf. It's easy to see AMD opted for core count over SMT strategy with Shanghai.It's less expensive from R&D pov,easier to design and is easier to validate(you just add more already proven cores at the time your process matures).Downside with Istanbul is a need for additional L1/L2 caches but it should add only about ~9mm2 of additional space on the die(7.5mm2 per MB of sram in 45nm Shanghai design)

Nothing comes cheap,SMT is no exception.I expect that Bulldozer cores feature some form of SMT(or maybe even DSMT?),but until then Shanghai/Istanbul/M. Course will do just fine.

Core size couldnt be more irrelevant. You seem to use it as an excuse for poor performance. What matters is performance, TDP, price. And AMD struggles hard in both. And as it is now you need 30.6mm2 of Shanghai cores size to even match a single nehalem 24.4mm2 core size in performance.

[informal]

Yeah whatever lol.Ignore the point and post one sentence reply in effort to quickly go over it since it doesn't fit well in your blue "world of performance"

Core size plays a huge role and Nehalem cores are huge for a reason.You will get the comparable perf. price and TDP with Istanbul,so let's see what your argument will be then

ninja edit on top of your ninja edit:
4x24.4 > 6x 15.3 ... Oh and perf. will scale linearly with Istanbul,while SMT is a different "beast" scaling excellent in some cases and hurting perf. in others. SO "matching" the perf. of one Nehalem core could be a bit of the understatement.

[Macadamia]

SMT is less of a rose garden than you think. It's good for threaded performance (deemed "free" but not actually) but a b*tch to validate, especially for server environments.

I'm opposed to AMD putting SMT in- rethinking the whole core methodology (instead of just building off previous stuff) could yield a much more desirable INT performance increase. And without fab ownership, AMD better execute fast and temporarily give up on SMT until it gets to a much better financial situation.

[mAJORD]

There's no denying that SMT is both great and a hinderence at the same time (for the validation reasons Mac points out, plus the extra core space).

therefore, what AMD needs to be able to do one of a few things.. or a combination of both:

Increase Raw single core IPC by at least 10% without increasing core size, and without increasing power consumption, both at a given node.
or
*Reduce L2 CAche size to 256Kb whilst reducing latency significantly
and/or
*Reduce L3 Latency significantly
and/or
*Increse cache density closer to intels standard - both L2 and 3

If they can either do 1 of the above really well, or a bit of all of the above THEN Informals argument will actually benefit AMD in reality. and they wont need SMT.


At the moment though, the fact is whilst AMD has a core size advantage, its not quite enough.. A six core Istanbul is a great solution against a 4 core Nehalem, but it's going to be bigger, won't match the clock speeds straight away, and thus will probably still lose to higher clocked nehalem.


I'm betting on a combination of most things I mentioned for the next Gen AMD core.. I DON"T think it will have SMT, and I don't think it will have significantly higher IPC / core.. increasing IPC too much is a dead end.. Utilising ways to increase MT performance, whether it's small, efficiecnt cores (AMD's most logical solution) or sophisticated SMT Cores (INtels current, and future solution) .

[savantu]

They surely are a competition. Istanbul scales to 48 cores. Nehalem to 32 with 64 threads (some say that double as much). Fight!

??

IBM xSeries scale to 16 sockets for Xeon ( older variants could do 32 sockets, not sure if this is still true ) .That is 96 cores.
If Nehalem EX based XSeries sticks to the same line , there would be 128 cores with 256 threads.Unisys offers a similar box with Dunnington, 16 sockets for a total of 96 cores.

From the looks of it , SGI will build a large Altix based Xeon, imagine 512 sockets with 8 cores/16 threads per socket.Problem is if they will be around when Beckton launches.

[ToTTenTranz]

Why drink soda? This is an expression I've never heard before.

[saaya]

wow, i didnt expect amd to surprise me!
this is good news! very good news!

and per socket cache indexing is a great addition!

now one thing i still dont understand, is when ati and the server department of amd will FINALLY realize that they are working on almost the same problems and connect to work together...

sideport? please! why would you add something so inferior if you have HT3.0 at your hands? driver based xfire? please! why would you do so basic and stupid thread and workload sharing when you have such a great workload sharing ip at your fingertips? and how can amd strugle with their ddr2 and ddr3 memory controllers when it was ati for the biggest part who invented those standards and has reat controllers for them?

[jagass]

More info about the Istanbul...

[Jacky]

Informal, what's your opinion on performance? Higher than 2P Nehalem? In those benches were Nehalem is already 30, sometimes even 50%, ahead (which are quite a lot according to Anandtech) it should be a toss-up. If performance scales linearly the 6 core might be 50% faster than its 4 core brethren, but it will have a serious clock deficit against mature nehalem chips.
Could dominate in linpack and virtualisation, though.

Are they going to implement high-k/metal gates and if yes, what can we expect?

I don't think AMD's approach/6c-architecture is superior to Intel's (it ain't), but it's viable and the good news for AMD is that the chip is on track. It won't necessarily dethrone Intel (even for a short period of time), but it certainly may faciliate AMD's long term survival and/or profitability (at least in this market segment).

[eric66]

great might buy this one cause of the name :P

[m^2]

??

IBM xSeries scale to 16 sockets for Xeon ( older variants could do 32 sockets, not sure if this is still true ) .That is 96 cores.
If Nehalem EX based XSeries sticks to the same line , there would be 128 cores with 256 threads.Unisys offers a similar box with Dunnington, 16 sockets for a total of 96 cores.

From the looks of it , SGI will build a large Altix based Xeon, imagine 512 sockets with 8 cores/16 threads per socket.Problem is if they will be around when Beckton launches.

Yeah, and Newisys Horus scales to 32 sockets (previous generation Opteron).
Cray Jaguar to thousands.
I meant only what the platform offers, not how others extend it. Such modifications are never mainstream and usually cost much more / socket.

[informal]

Informal, what's your opinion on performance? Higher than 2P Nehalem? In those benches were Nehalem is already 30, sometimes even 50%, ahead (which are quite a lot according to Anandtech) it should be a toss-up. If performance scales linearly the 6 core might be 50% faster than its 4 core brethren, but it will have a serious clock deficit against mature nehalem chips.
Could dominate in linpack and virtualisation, though.

Are they going to implement high-k/metal gates and if yes, what can we expect?

I don't think AMD's approach/6c-architecture is superior to Intel's (it ain't), but it's viable and the good news for AMD is that the chip is on track. It won't necessarily dethrone Intel (even for a short period of time), but it certainly may faciliate AMD's long term survival and/or profitability (at least in this market segment).

Good questions Jacky.
2P performance crown will be decided by the frequency target of Istanbul.*IF* AMD can get the clocks to ~2.8-3Ghz range and 105W ACP ,then I'd say it should be comparable to 2.93-3.2Ghz Nehalem EP.
Nehalem does have a few "bonuses"s so to speak,Turbo and tri channel DDR3 being few .But SMT is double edged sword and even though intel may still hold ie. top SAP scores(one case where SMT has stellar showing),on some other types of workloads Istanbul may end up faster even with lower clocks-due to before mentioned linear scaling with cores.Also the new probe filter helps quite a bit in some workloads as we can see from the demo-1.68x more perf. with 1.5x more cores that work on somewhat lower clocks.

Linpack and virtualization as you said will probably be the strong points of Istanbul.Also the platform is already validated and CPUs will be drop in replacement which is a big plus.

As for high k/mg AMD said they might go with "gate first" approach when it comes to mg technology.As for high-k I'm not sure.
Indeed 6c version of Shanghai is not superior to Nehalem from a strict uarch. POV,but is comparable.SMT in Nehalem is *very* complex piece of technology.But on the integration front,looking at both 45nm designs,they are comparable.AMD and intel had different approaches this time around,one being more smaller cores strategy while the other less but more complex cores strategy. In single thread int. workloads both designs are similar in perf. with Nehalem having an edge(5-10%).

[saaya]

horus never made it tho, afaik it was cancelled... too bad, the idea was great, they had potential...

jacky, yes, i think nehalem will beat even these 6 core opterons, but keep in mind that these are ddr2 and fit into existing infratructure, so you can upgrade the cpus and leave the rest of the server the same, simply boosting the performance. thats a nice feature...
in the end even a performance diference of 20% is still not that important to most customers, they can live with that.
youd be surprised how many companies upgrade old servers even though it barely gives them a boost, but its too time consuming and annoying to switch to a completely new server setup, uprading is usually a plug and play thing, and beeing able to upgrade from 4 slow to 6 fast cores is very nice.