Intel TAT / CoreTemp / IDCC all different temperatures....

[coldpower27]

My Delta to Tjunction at load is about 25 Degrees, with it being 50 Degrees at idle.

[unclewebb]

Here's a guy on the [H] forum that decided to take my test using his E6400 revision L2.

http://www.hardforum.com/showpost.ph...3&postcount=87

Though his heatsink and fan are far superior at cooling then my OEM heatsink and fan, he ended up with the exact same results.
His absolute core temperature with an assumed Tjunction of 85C was equal to his ambient temperature.

The assumed Tjunction of 100C that CoreTemp 0.95 uses for his L2 E6400 processor doesn't seem right. That's all I'm really trying to prove.

joebuffalo: "You assume that the air inside your case is the same temperature as the air outside the case.

No I didn't. The case was open and the temperature probe was beside the cpu fan.

"You are assuming that Tjmax is either 85 or 100.""

The Core2Duo mobile processors with the exact same CPUID of 6F6 have a documented TjMax of a fixed 100C or 85C. Why would Intel change their manufacturing process for the Core2 Duo desktop processors that have the same 6F6 CPUID? They're the same processor built on the same manufacturing process. The only difference is the packaging they're shoved into with a different pin count for a mobile or desktop application.

Assuming TjMax isn't a fixed value of 85C or 100C is no different than assuming it is a fixed value. Until documentation is released by Intel to clarify this, neither side can be proven to be right or wrong.

Try taking my Tjunction test and let's see what kind of results you get. I'm very interested in results from E4300 users.

[joebuffalo]

No offense, unlcewebb, but not only will I not take your test, I will advise others against taking your test. It confuses the matter (for those that don't understand Core2 temperature readings) and serves no purpose (for those that do understand Core2 temperatures).

The only thing anybody with a Core2 Duo desktop processor should do is read their DTS directly from CoreTemp 0.95

[joebuffalo]

But don't you find it strange that the "Delta to Tjunction" throttle point with the quad core co-incides exactly with the software written Tjunction value of 100C?

Actually, it makes *perfect* sense:

The software reads the DTS directly from the CPU as '55'
The software *assumes* a tjmax of '100'
The software *calculates* a core temperature of '45'

[cmos.gr]

Why not just use the ''clasic'' diode from PECI ?...

Mine results with an 6400 at 3600@ 1.417v watercooled 24C room 26-27C Radiators(3x dual nexXxos) are...

idle core temp 39-41c (ok i will tell the max of one core only)
idle PECI from AI SUITE 32-33

Full load orthos after 30s
Full core temp : 65c
Full PECI AI SUITE 55C

After some tests i realize that core temp was WRONG.It says 10C More under load and 7-8C on idle.

In my opinion if all previous posts are right them...coretemp is just for some cores/cpus.

[kwalker]

Why not just use the ''clasic'' diode from PECI ?...

Mine results with an 6400 at 3600@ 1.417v watercooled 24C room 26-27C Radiators(3x dual nexXxos) are...

idle core temp 39-41c (ok i will tell the max of one core only)
idle PECI from AI SUITE 32-33

Full load orthos after 30s
Full core temp : 65c
Full PECI AI SUITE 55C

After some tests i realize that core temp was WRONG.It says 10C More under load and 7-8C on idle.

In my opinion if all previous posts are right them...coretemp is just for some cores/cpus.

One reason you won’t be able to rely on the PECI reading of the on die thermal diode is that Intel has discontinued or disabled the Diode on newer CD2 processors and only the DTS is used for thermal management and fan control...
Perhaps better support is inevitable for developers of software monitoring core temperature.
Every processor package varies slightly and T-junction being set per package during manufacturing and not software readable makes this a chore to determine the actual thermal design limit.
If you run Ortho’s for any length of time at max load you will notice the margin of error is less from core temp to the diode reading and this varies from build to build.
For now that’s what we have and it is not perfect
In some cases just wrong.
I rely on the motherboard software more than Core temp because of the discrepancies.
If it’s stable why worry.

[cmos.gr]

uhm so...

If someone want to see if his core temp or any prog reports right temperature the only thing he has to do is to stop his cooler's fan or pump for watercool and see if at 85 (reported) temp his CPU will start throttling..
If yes then temp progs like core temp are fine.

Right ?

Edit:

I just test mine and...
At reported temp of 83C° (core temp) cpuz gone from 2128mhz to 1600mhz (default 6400 to make sure TM is working fine)

Now what ? The right temp is not only higher (than PECI) but +2C° more than core temp's reported temperature ?

Sh..t thats TOO bad uh ? :S :S :S

[kwalker]

In theory Yes.
If your a brave soul

[cmos.gr]

Lol thats not a prob..ill not cry for them :P

Ok so test # 2 (from a guy at hard forums)

266fsb*6multi@ 1.07vcore.

Radiator Temperature 25C (+-1 or 2 cause its from a gatewatch panel...(i need to find fast a good tool for temp)
IDLE
Motherboard temp(or peci I really don't know wtf is that temp) : 24C (impossible ?! but NEAR radiator temperature)

Core 1 :31C
Core 2 :30C

Its +- 5C° more than radiator temperature.
I cant believe this can be right with these settings.Only 1600mhz and 1.07vcore IDLE...

Argh I'm confused
Or finaly I must say to my self that I have a really hot chip.what can I say :S

[kwalker]

Those temps seem to be in line considering the applied voltage.
As for core temp TAT or speed fans functionality I’ll do a quick comparison between platforms.
My core duo lap top with TAT or Orthos running full load and no overclock the temperature reported by TAT and core temp never exceed 47C .
This is in a little flat black box with virtually no air flow and a heat pipe with a fan on the end exhausting out the back..
Using TAT and core temp in my desktop with excellent air flow and high a high end liquid cooling solution the temperatures will soar upward of 60C(TAT) 51C orthos.
This could be the fact that TAT was designed for the mobile platform and similarly core temp seems to be more accurate at low applied voltages or higher clocks at max load.
The discrepancy I have noted is in the area where Fan speed control is commanded or TCC activation.
Is core Temp accurate?
In many cases yes.
Then again Intel states that the Bios or Intel interrogator software is accurate within 3C.
Some how I believe in the very near future you will see Core temp to be very reliable but at this time there is no 100% accurate temperature reporting utility.
Like I said before
If its stable why worry.

[cmos.gr]

That was a nice example...

Only a word on this

If its stable why worry.

If it was stable at your temp ( 51C orthos )I wont say anything...
But here I see a 8-10C difference between 3 Sensors (numbers lets say better).

Please if anyone can to this test...post his results.
Post the CPU , Core 0 and Core 1 idle from SpeedFan 4.32
Then
Enable PECI from bios and post the same temps Cpu, core 0 and core 1.
I test that in 2 systems with same mobo different cpus and i got different results.
On my system CPU temp (peci anyway) had +-10 temp less than core 0-1
On other system CPU temp was exactly the same with core 0-1.

And one more thing.
Tjunction is at 85C ?Thats a standard ? 100% ?
Lets say...it cant be at 80 ? so coretemp or any program uses DTS report wrong temp ?Cause mine for example was not as 85 but in 83 (IF temp was right then why Tjunction enabled at 83 and not at 85 for my cpu?... )

I'm really stuck on that now

[joebuffalo]

Here are the things we know 100% for certain regarding Core2 Temperatures:

1. Nobody knows for sure what the Tjmax is for a Core2 Desktop Processor

2. DTS readings are always 99% percent accurate and should not be questioned

3. CoreTemp 0.95 can be configured to display DTS readings directly

4. Absolute temperatures are unnecessary and confusing. Learn to embrace DTS.

[cmos.gr]

2. DTS readings are always 99% percent accurate and should not be questioned

So why I have still 2-3 C to Tjunction but CPU started already?
Who says that the real Tjuncton isn't at 75C ?(at this temp +- (i don't remember for sure)reported from Tcase diode.)
CoreTemp still calculates with report point 85C which isn't the real Tjunction.

And if..

3. CoreTemp 0.95 can be configured to display DTS readings directly

DTS readings (from CoreTemp)in my case are wrong.
I tested.
Its just the reverse

[fgw]

So why I have still 2-3 C to Tjunction but CPU started already?

first of all, on desktop and server processors the reference point used is not tjunction but tcc (thermal control circuit) activation temperature instead! tjunction is used on mobile processors only.
i know coretemp is calling this reference temperature tjunction on all processors. tat does the same, but as tat is designed for mobile processors only it is naming this reference temperature correct. guess thats the reason many people call this reference point tjcunction.
anyway, this does not change anything in the resulting temperatures ...

so why have you seen throttling starting at a coretemp reading of 83C? coretemp uses a sample rate of 1 second by default. the last time coretemp read the dts value coretemp might have read 2C and thus calculated 83C absolute temperature, but as dts and tcc reacts very fast it started throttling even before coretemp was able to read the next dts value a second later.
you can try to set the temperature read interval in coretemp to a lower value and you might see different temperatures where throttling starts.

besides that, the temperature where tcc gets activated is calibrated during manufacturing on a per part basis and thus might differ from processor to processor. regardless of coretemp, which will read anything near 85C or near 100C (depending on the assumed reference temperature), your processor might start throttling at 83C, 84C or even 87C. you simply cant tell, cause its impossible to convert dts readings into an absolute temperature.

thats the reason i requested the display of plain dts values through coretemp. which was implemented in coretemp095. instead of trying to keep your processor below a certain temperature you should try to keep dts readings ABOVE a certain value which means staying away from tcc activation by this value.

Who says that the real Tjuncton isn't at 75C ?(at this temp +- (i don't remember for sure)reported from Tcase diode.)

there is no tcase diode in c2d processors! the td (thermal diode) you are referring is like the dts (digital thermal sensor) located on the die itself and thus reports processor temperature directly from the die. the dts has a smaller foot print than the td and thus can be located closer to hotspots on the die. also dts reacts very fast and dts temperatures can be read directly as a 7bit value from a register. in contrast td needs two pins on the processor socket where an electric signal can be measured which needs to be calibrated and converted into a temperature! thus accuracy of temperature readings via td rely on calibration ond conversion. as this is done in bios, its up to the bios what temperatures are read via td. the bios might calibrate this temp to simulate a temperature similar to tcase definitions by intel or it might be calibrated to simulate a temperature which is close to core temperatures. you simply don't know what the bios writer had in mind.

regarding tcase:
intel defines tcase as the temperature measured at the geometric center of the ihs on top of the ihs surface! there is no temperature sensor nor a diode reporting this temperatur. it's just a place outside the processor where temperatures may be measured ...

CoreTemp still calculates with report point 85C which isn't the real Tjunction.

And if..

DTS readings (from CoreTemp)in my case are wrong.
I tested.
Its just the reverse

as dts temperatures are an offset to tcc activation, coretemp as all other software using dts has to calculate absolute temperatures by subtracting dts readings from tcc activation temperature. the problem here is this tcc activation temperature, as mentioned above, is different from part to part and once configured during manufacturing can't be changed nor read out by any software! this tcc activation temperature simply has to be assumed somehow!
on mobile processors a bit in a register exists which tells if tjunction (which is used on mobile processors only) is at 85C or at 100C.
this bit is NOT valid on desktop and server processors. depending on the content of this single bit, temp monitoring software assumes if 85C or 100C has to be used in subsequent calculations. this assumption might be close to reality on many processors, but definitely is about 15C off on some other processors.

DTS readings are always 99% percent accurate and should not be questioned

yes, DTS readings are correct! the problem is in the conversion into absolute temperature values as explained above. here comes inaccuracy into play ...

[SLi_dog]

DTS readings (from CoreTemp)in my case are wrong.
I tested.
Its just the reverse

I originally thought that this was the case as well but according to the creator of CoreTemp, the configured "Delta to Tjunction" temperature are direct DTS readings only, no calculation is involved.

3. CoreTemp 0.95 can be configured to display DTS readings directly

Seems you were right Joe

[unclewebb]

so why have you seen throttling starting at a coretemp reading of 83C? coretemp uses a sample rate of 1 second by default. the last time coretemp read the dts value coretemp might have read 2C and thus calculated 83C absolute temperature, but as dts and tcc reacts very fast it started throttling even before coretemp was able to read the next dts value a second later.

I think what cmos.gr has noticed is that processor throttling begins at a CoreTemp 0.95 DTS value of 2.

By controlling the cpu fan speed I can bring the temperature up very gradually and TAT will first report "Thermal Monitor Active" in red when DTS=2. RightMark also reports at this point "CPU core overheat detected" and shows that some form of throttling is taking place.

By adjusting the fan speed I can hold DTS=2 without letting it ever get to zero. If I turn up the fan speed a little to cool things down, as soon as CoreTemp reports DTS=3, the TAT Thermal Monitor Active light turns back to green and changes to Thermal Monitor Idle.

This testing seems to show that processing power first gets reduced at DTS=2. I don't think the TAT reported MHz gets reduced until DTS=0 but that doesn't mean that the processor isn't already throttling.



Note: Just to clear things up. I booted up at 425 X 8 = 3400 MHz and then used ClockGen to reduce it to 400 X 8 = 3200 MHz for better stability at full load and full temp before starting this test. CoreTemp reports the wrong MHz but the 3200 MHz in TAT is correct. This first level of throttling does not reduce the reported 3200 MHz the processor was originally running at.

On a side note, does anyone know why TAT grays out CPU1 sometimes as in the above picture?

[cmos.gr]

Actually my cpu reduced mhz at DTS = 2

I think your setup/configure is not able to slow down your processor...

This happen to me..Only with default setting it could slow down cpu speed.

[unclewebb]

I did another test and this time I let the temperature go higher until DTS=0.

TAT held steady at 3200 MHz but CPUz showed it being reduced to 3167 MHz and once it dropped down to the low 2000 MHz range but I missed a screenshot of that.

CoreTemp showed that the VID had been reduced from 1.325 to 1.1625 volts. SpeedFan and CPUz showed the core voltage steady at 1.392 volts so the Asus P5B might lock the CPU voltage and ignore any requests to lower it when it is not set to AUTO in the bios.

TAT and SpeedFan occasionally reported absolute temps of -40C to -42C when the temps seemed to go higher.

[joebuffalo]

Wow, now that's a hot processor!

This is interesting work you are doing and I it will surely help us to better understand the Core2 Desktop processors. I would point out though that these new observations should not be misconstrued as evidence that the DTS reading is innaccurate. I made notes before of when other people who ran their processors to crazy high temps like you. I'll see if I can find those so we can do some comparisons.

Do you have both TM1 and TM2 enabled in your BIOS (or maybe they are disabled in some software - I do know I've seen check-boxes for these in RightMark)? That could possibly affect what happens as you approach DTS=0.

[joebuffalo]

Here is one link where sombody else saw throttling at DTS=2:

http://forumz.tomshardware.com/hardw...588903#1588903

[joebuffalo]

I had not seen this doc before (though you posted the link a long time ago) so I thank you for that unclewebb.

http://www.intel.com/design/processo...als/253668.pdf

Reading this document makes it clear that if we have a clever programmer and an intrepid tester, we can learn a lot about how this stuff is working. That MSR contains a lot of info: has thermal monitoring taken place recently? the ability to enable thermal throttling via software, etc. Very interesting.

[joebuffalo]

I had mentioned a few days (weeks?) back that I thought that the Tj_max was *individually* set for *each* processor. If that were the case, we can all agree that absolute temperature are ABSOLUTELY POINTLESS, right? If you have no clue what Tj_max is, you can never accurately convert a DTS reading into an absolute temperature. NEVER. Do we agree?

Good. Now read this. I can't believe I read this like a month ago and totally forgot about it. I should have shared this with more people. It's a MUST READ for those who want to understand Core2 temperatures.

http://documents.irevues.inist.fr/bi...79/1/TMI23.pdf

Allow me to quote my two favorite lines:

"To achieve measurement accuracy, each sensor is calibrated at test time. Calibration is done for the Maximum Tj and the linearity of the readout slope. The temperature reading is post processed for filtering out random noise and generating the H/W activated thermal protection functions."

and

"The DTS is calibrated at manufacturing conditions and the reference point is set to this test temperature. Functionality, electrical specifications and reliability commitments are guaranteed at maximum Tj as measured by the DTS. Any test inaccuracy or parameters variance are already accounted for in the DTS set point"

Allow me to summarize: Absolute temperture *calculations* on Core2 processors are *pointless*. DTS *readings* are accurate and factory calibrated.

Embrace DTS.

[joebuffalo]

While I'm at it I might as well link to everything else useful I've collected on this topic:

http://www.intel.com/design/core2duo/documentation.htm

http://www.intel.com/technology/itj/...sign_point.htm

http://www.intel.com/technology/itj/...management.htm

ftp://download.intel.com/design/inta...d/31527902.pdf
Intel® CoreTM 2 Duo E6400 and E4300 Processors for Embedded Applications

4.2.10 Digital Thermal Sensor
The Intel® Core™2 Duo desktop processor E6000 sequence introduces the Digital
Thermal Sensor (DTS) as the on-die sensor to use for fan speed control (FSC). The DTS
will eventually replace the on-die thermal diode used in pervious products. The
processor will have both the DTS and thermal diode enabled. The DTS is monitoring the
same sensor that activates the TCC (Refer to Section 4.2.2). Readings from the DTS
are relative to the activation of the TCC. The DTS value where TCC activation occurs is
0 (zero).
The DTS can be accessed by two methods. The first is via a MSR. The value read via the
MSR is an unsigned number of degrees C away from TCC activation. The second
method which is expected to be the primary method for FSC is via the PECI interface.
The value of the DTS when read via the PECI interface is always negative and again is
degrees C away from TCC activation.

4.2.2 Thermal Control Circuit
The Thermal Control Circuit portion of the Thermal Monitor must be enabled for the
processor to operate within specifications. The Thermal Monitor's TCC, when active, will
attempt to lower the processor temperature by reducing the processor power
consumption. In the original implementation of thermal monitor this is done by
changing the duty cycle of the internal processor clocks, resulting in a lower effective
frequency. When active, the TCC turns the processor clocks off and then back on with a
predetermined duty cycle. The duty cycle is processor specific, and is fixed for a
particular processor. The maximum time period the clocks are disabled is ~3 µs. This
time period is frequency dependent and higher frequency processors will disable the
internal clocks for a shorter time period. Figure 7 illustrates the relationship between
the internal processor clocks and PROCHOT#.
Performance counter registers, status bits in model specific registers (MSRs), and the
PROCHOT# output pin are available to monitor the Thermal Monitor behavior.

4.2.3 Thermal Monitor 2
The processor supports an enhanced Thermal Control Circuit. In conjunction with the
existing Thermal Monitor logic, this capability is known as Thermal Monitor 2. This
enhanced TCC provides an efficient means of reducing the power consumption within
the processor and limiting the processor temperature.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the
enhanced TCC will be activated. The enhanced TCC causes the processor to adjust its
operating frequency (by dropping the bus-to-core multiplier to its minimum available
value) and input voltage identification (VID) value. This combination of reduced
frequency and VID results in a reduction in processor power consumption.






ftp://download.intel.com/design/proc...s/31327803.pdf

Intel® Core2 Extreme Processor X6800 and Intel® Core2 Duo Desktop Processor E6000 and E4000 Sequences

5.1.1 Thermal Specifications

5.2.4 PROCHOT# Signal

An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has reached its maximum operating temperature. If the Thermal Monitor
is enabled (note that the Thermal Monitor must be enabled for the processor to be
operating within specification), the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or deassertion
of PROCHOT#.
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that one or both cores has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will
remain active until the system de-asserts PROCHOT#.




5.2.5 THERMTRIP# Signal

Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
Table 26). At this point, the FSB signal THERMTRIP# will go active and stay active as
described in Table 26. THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles.


Tabel 26

THERMTRIP#

In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a
temperature approximately 20 °C above the maximum TC.
Assertion of THERMTRIP# (Thermal Trip) indicates the processor
junction temperature has reached a level beyond where permanent
silicon damage may occur. Upon assertion of THERMTRIP#, the
processor will shut off its internal clocks (thus, halting program
execution) in an attempt to reduce the processor junction
temperature. To protect the processor, its core voltage (VCC) must
be removed following the assertion of THERMTRIP#. Driving of the
THERMTRIP# signal is enabled within 10 µs of the assertion of
PWRGOOD (provided VTT and VCC are valid) and is disabled on deassertion
of PWRGOOD (if VTT or VCC are not valid, THERMTRIP#
may also be disabled). Once activated, THERMTRIP# remains
latched until PWRGOOD, VTT, or VCC is de-asserted. While the deassertion
of the PWRGOOD, VTT, or VCC will de-assert THERMTRIP#,
if the processor’s junction temperature remains at or above the trip
level, THERMTRIP# will again be asserted within 10 µs of the
assertion of PWRGOOD (provided VTT and VCC are valid).

5.3 Thermal Diode

The processor incorporates an on-die PNP transistor where the base emitter junction is
used as a thermal "diode", with its collector shorted to ground. A thermal sensor
located on the system board may monitor the die temperature of the processor for
thermal management and fan speed control. Table 31,Table 32, and Table 33 provide
the "diode" parameter and interface specifications. Two different sets of "diode"
parameters are listed in Table 31 and Table 32. The Diode Model parameters (Table 31)
apply to traditional thermal sensors that use the Diode Equation to determine the
processor temperature. Transistor Model parameters (Table 32) have been added to
support thermal sensors that use the transistor equation method. The Transistor Model
may provide more accurate temperature measurements when the diode ideality factor
is closer to the maximum or minimum limits. This thermal "diode" is separate from the
Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the
Thermal Monitor.




http://download.intel.com/design/pro...x/31368502.pdf

Intel® Core™2 Duo Desktop Processor E6000? and E4000? Sequence Thermal and Mechanical Design Guidelines

4.2.10 Digital Thermal Sensor
The Intel® Core™2 Duo desktop processor E6000/E4000 sequence introduces the
Digital Thermal Sensor (DTS) as the on-die sensor to use for fan speed control (FSC).
The DTS will eventually replace the on-die thermal diode used in pervious products.
The processor will have both the DTS and thermal diode enabled. The DTS is
monitoring the same sensor that activates the TCC (see Section 4.2.2). Readings from
the DTS are relative to the activation of the TCC. The DTS value where TCC activation
occurs is 0 (zero).
The DTS can be accessed by two methods. The first is via a MSR. The value read via
the MSR is an unsigned number of degrees C away from TCC activation. The second
method which is expected to be the primary method for FSC is via the PECI interface.
The value of the DTS when read via the PECI interface is always negative and again is
degrees C away from TCC activation.

[joebuffalo]

OK, I was re-reading the info in the above post. Important line to read: "The DTS value where TCC activation occurs is 0 (zero)."

[cmos.gr]

So...When someone see DTS=0 that doesn't mean his cpu is at 85C.
He may have 60C...or 70C or 80C or 90C.

Right ?