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Thread: AMD Dual-Core Toledo Socket939 CPU-Z Pciture

  1. #101
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    Thank you sxs112.
    http://www.c627627.com/AMD/Athlon64/
    (Refresh)
    Last edited by c627627; 04-14-2005 at 11:49 PM.

  2. #102
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    Quote Originally Posted by shuRe
    gwan sxs112 if you can post all these screenies of the toledo then you can do a little bit of overclocking on stock cooler. plz
    Don't think he can OC because of the mobo..

  3. #103
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    Quote Originally Posted by furyfax
    Don't think he can OC because of the mobo..
    my bad

  4. #104
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    sxs112, why don't you give GCPUID a shot, see how it works with your new chip?
    Download GCPUID here
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  6. #106
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    the cache is shared between the cores, physically its one block of cache from what i have seen, and the cores use HT links to access it
    Quote Originally Posted by bh2k
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  7. #107
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    No its not, they are two seperate cores.
    How hard is it to believe? they are two seperate K8 Venice/San Diego cores connected at the memory controller.
    Attached Images Attached Images
    Last edited by The Coolest; 04-15-2005 at 03:46 AM.
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  8. #108
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    Quote Originally Posted by reject
    the cache is shared between the cores, physically its one block of cache from what i have seen, and the cores use HT links to access it
    sorry. but there is no way that's right. why would they take up die space making an slow HT link between the cache and core now when they never did before?
    it's two seperate caches. i think all the cores will be made with 1mb+1mb, but any of them with a defect in the cache (likely, due to size) get cut down to 512kb+512kb
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  9. #109
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    hmm so according to the newer roadmap only the 4800+ has 2mb of L2 and both the 4600+ and the 4800+ are 2.4 ghz.

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    Quote Originally Posted by ozzimark
    sorry. but there is no way that's right. why would they take up die space making an slow HT link between the cache and core now when they never did before?
    it's two seperate caches. i think all the cores will be made with 1mb+1mb, but any of them with a defect in the cache (likely, due to size) get cut down to 512kb+512kb
    Look at the picture in the post above yours. You're right, these are 2 seperate processing cores, with their own dedicated L1 and L2 caches, and the only place they meet is the memory controller.
    I have to disagree with you on your statement that all cores will be 1mb+1mb, when clearly, already its not the case.
    20F30 is a CPUID reading of a dual core 1MB+1MB CPU, the new DC Opteron have a 20F10 CPUID reading. The chip we see in this thread is 20FB1, which is not similar to either of these CPUIDs.
    The 20F30 and 20F10 are like 2 San Diegos stuck together, this 20FB1 is like 2 Venices stuck together, there is no disabled L2 cache on this chip. I don't think I've ever seen an ES (and this is a semi-ES as it doesn't have a model number programmed into it, that's why the BIOS reads it as 2200+) that had disabled cache, or been disabled by any other means.
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  11. #111
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    Quote Originally Posted by The Coolest
    Look at the picture in the post above yours. You're right, these are 2 seperate processing cores, with their own dedicated L1 and L2 caches, and the only place they meet is the memory controller.
    No, they meet at the crossbar, the System Request Queue. This in turn is connected to the HT links and the memory controller. So CPU-CPU cache snooping traffic never goes out to the HT links, like in a dual CPU system. This improves performance slightly.

    Code:
      MC      HT
        \    /
         SRQ
        /    \
    core1   core2
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  12. #112
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    Quote Originally Posted by LowRun


    According to this news dual core A64 could take advantage of Hyper Threading: http://www.x86-secret.com/index.php?...=newsd&nid=871
    Not exactly. An AMD dual core CPU will be able to *appear* as a single core with HT support. This is because some morons develop software for HyperThreading, but fail to spawn threads for multi-CPU. By appearing as a HT CPU an AMD dual core would be able to take advantage for HT-aware Dual-UNaware software.
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  13. #113
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    Pjotr>> Yes you're right on the fact that there's System Request Queue between the cores and the memory controller. But what I wanted to say basically is that the CPUs are still two completely seperate cores.
    HyperThreading is relatively old tech, dual core is relatively new, not all developers that were writing their programs for multi CPU support, never knew about Intel and AMD releasing multi-core CPUs in the future, so this feature allows older software to still have a noticable performance increase over running on a single core.
    So I wouldn't call developers morons just because they didn't know about this.
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  14. #114
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    my question is, how can we overclocked it?

    independent clock speed for each core, or just one for both? ummm I think 1, since it only have 1 mem controller and independent clock speed adjustment for each core is somewhat not logic

  15. #115
    Quote Originally Posted by c627627
    Believe it or not, that roadmap is not based on emotion.

    Here's the thought process on the particular point you raised so a counter argument could be offered:

    Since it appeared that we would see a 3 GHz 90nm single-core Opteron in Q1 2006, it was safe to assume that we would see a 3 GHz Athlon 64 FX and by extension 3.2 GHz Athlon 64 FX.

    Ed Stroligo of overclockers.com seemed to think so and he's got a pretty good conservative track record.

    His views from a couple of weeks ago mentioning this very argument are here: "Here Comes 3"
    .
    .

    To sell a part at 3.2, it needs to run at 3.4, at least, with no problems. This is known as a "guard band". I'm not sure 90nm will deliver that, especially by Q106.

    It's also pure speculation, not really a "roadmap". Perhaps you should cite the evidence you have for each prediction on your website with a link to an explanation somewhere else on your site. That way, folks can distinguish between supposedly leaked roadmaps and speculation.

    Oh, and I wouldn't rely on the Ediot for anything.

  16. #116
    Quote Originally Posted by sxs112
    New BIOS

    Athlon64 X2 Dual Core Processor 2200+(4400+)
    Well this is strange.

    If 4400 = 2 x (2.2GHz, 512K L2)
    and (speculating) 4800 = 2 x (2.4GHz, 512K L2)

    What the heck is 4600? Are they really going to release 2.3GHz cores? I guess that's possible, and perhaps makes some sense, even.

    The alternative of: 4600 = 2 x (2.4, 512K L2), 4800 = 2 x (2.4, 1MB L2) is possible, but it doesn't make as much sense from the model number viewpoint.
    Last edited by terrace215; 04-15-2005 at 09:24 AM.

  17. #117
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    Quote Originally Posted by terrace215
    Well this is strange.

    If 4400 = 2 x (2.2GHz, 512K L2)
    and (speculating) 4800 = 2 x (2.4GHz, 512K L2)

    What the heck is 4600? Are they really going to release 2.3GHz cores? I guess that's possible, and perhaps makes some sense, even.

    The alternative of: 4600 = 2 x (2.4, 512K L2), 4800 = 2 x (2.4, 1MB L2) is possible, but it doesn't make as much sense from the model number viewpoint.
    I think 4600+ is 2.4Ghzs 512Kb cache and 4800+ 2.4Ghzs 1Mb Cache.

  18. #118
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    Quote Originally Posted by terrace215
    Well this is strange.

    If 4400 = 2 x (2.2GHz, 512K L2)
    and (speculating) 4800 = 2 x (2.4GHz, 512K L2)

    What the heck is 4600? Are they really going to release 2.3GHz cores? I guess that's possible, and perhaps makes some sense, even.

    The alternative of: 4600 = 2 x (2.4, 512K L2), 4800 = 2 x (2.4, 1MB L2) is possible, but it doesn't make as much sense from the model number viewpoint.
    Its very possible that this is what's going to happen:
    4200+ = 2.0GHz 2x512KB <-- Might not happen at all.
    4400+ = 2.2GHz 2x512KB
    4600+ = 2.4GHz 2x512KB
    4800+ = 2.4GHz 2x1MB

    I think that at least for now, both of the dual core CPUs are going to be called Toledo, as we don't have any other info on this.
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  19. #119
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    or, it could be that
    4400+ = 2.2 GHz 2x512KB
    4600+ = 2.2 Ghz 2x1MB
    4800+ = 2.4 Ghz 2x512mb
    and maybe a higher version later on with 2x1MB

    This is analagous to the new Venice and San Diego cores w/
    3500+ = 2.2 Ghz 512k
    3700+ = 2.2 Ghz 1MB
    3800+ = 2.4 Ghz 512k

    Just MHO.

  20. #120
    Quote Originally Posted by Orthogonal
    or, it could be that
    4400+ = 2.2 GHz 2x512KB
    4600+ = 2.2 Ghz 2x1MB
    4800+ = 2.4 Ghz 2x512mb
    and maybe a higher version later on with 2x1MB

    This is analagous to the new Venice and San Diego cores w/
    3500+ = 2.2 Ghz 512k
    3700+ = 2.2 Ghz 1MB
    3800+ = 2.4 Ghz 512k

    Just MHO.
    Not if you accept the italian site CPUZ shot, which featured:

    2.4GHz 2x1MB

    It would be odd to be sampling a part this far in advance that wasn't going to be part of the launch (and thus probably the 2400+/4800+ A64 X2)
    Last edited by terrace215; 04-15-2005 at 11:02 AM.

  21. #121
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    Of course I could be way off my rocker. If AMD is going to have the 4800+ as their new Flagship, it would most certainly have 2x1MB, if any at all have that much.

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    Quote Originally Posted by The Coolest
    HyperThreading is relatively old tech, dual core is relatively new, not all developers that were writing their programs for multi CPU support, never knew about Intel and AMD releasing multi-core CPUs in the future, so this feature allows older software to still have a noticable performance increase over running on a single core.
    Yes. But HyperThreading is rather new, while dual core is over ten years old. It's not a new phenomenon.

    So I wouldn't call developers morons just because they didn't know about this.
    I'm a developer and I would. Anyone programming threads based on number of CPUs *should* ask the system how many CPUs there are. They should *not* check if there is HT and forget to check for multiple CPUs. That's just stupid and I would slap my developers if they did that.
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  23. #123
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    Have you actually take the time to read how dual core works?
    on the Intel side, which has HT, makes it a bit more complex:
    First find out how many processors windows detects.
    Then find out how many cores a single chip has.
    Then find out how many virtual CPUs a single chip has.
    Then find out which CPU is a virtual and which one is physical.
    Build a list of which virtual CPU belongs to which physical, then make softare make the correct decision on what specific CPU to start a new thread....
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  24. #124
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    Except programmers are stereotypically lazy and will ask if the machine uses HT and not do any other checks. Which is obviously stupid/bad programming.
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    Quote Originally Posted by Adamantine
    Except programmers are stereotypically lazy and will ask if the machine uses HT and not do any other checks. Which is obviously stupid/bad programming.
    if you program multithreaded, this shouldn't be a problem ?

    compilers don't have to be adjusted either, do they ?or am i mistaking here ?
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