!!!The Ultimate K8L Thread 2007 & Beyond!!!

[MAS]

The Brisbane core's L2 latency should be 14 cycles, up from 12 cycles and not 20 cycles."

it's old news - Sharikou even sent Anand to school -)

[Shintai]

The guy has more knowlegde then you, that's for sure

Because he tells you want you hope to hear?

[alucasa]

Because he tells you want you hope to hear?

Blind faith, isn't it ...

[Shintai]

From the AnandTech article you link:

"Although AMD previously did not mention any issues with our findings, we were contacted today and informed that the latency information both ScienceMark and CPU-Z produced is incorrect. The Brisbane core's L2 latency should be 14 cycles, up from 12 cycles and not 20 cycles."

I find it funny if it should be incorrect. Its a very simple and basic test to find out the latency. But again, as gaming benchmark shows. Should and is aint always the same when a 4600(90nm) runs in circles around a 4800(65nm).

http://www.firingsquad.com/hardware/...view/page5.asp

And since K8 is hardly memory bandwidth constrained. Something else leads to this high difference (And obvious mislabeling).

[Shintai]

Blind faith, isn't it ...

Yep and its sad...

Also I wonder when nn_step will post AMDs official announcement that K8L gonna use ZRAM.

http://www.xtremesystems.org/forums/...32&postcount=8

I mean, he states they are. Tho its barely on the research table and K8L is tapped out...

[Serge84]

No serge, unless AMD themselves dont know what they talk about. AMD said that K8 65nm is 20 cycle. Also, 3ns is NOT 3 cycles.

http://www.anandtech.com/cpuchipsets...spx?i=2893&p=3

http://www.anandtech.com/cpuchipsets...spx?i=2893&p=3

Updated - 1/5/07: Although AMD previously did not mention any issues with our findings, we were contacted today and informed that the latency information both ScienceMark and CPU-Z produced is incorrect. The Brisbane core's L2 latency should be 14 cycles, up from 12 cycles and not 20 cycles. This would help explain the relatively low impact on application performance that we've seen across the board. We are still waiting to hear back from AMD on a handful of other issues regarding Brisbane and will update you as soon as we have more information.

The original K8 core, in both 130nm and 90nm flavors, had a 12-cycle L2 cache. With Brisbane, as reported by both CPU-Z and ScienceMark, 65nm K8 now has a 20-cycle L2 cache. Generally speaking you move to a higher latency cache if you're planning on introducing a larger cache size, but a quick glance at AMD's roadmaps doesn't show anything larger than a 1MB L2 per core for the next year. The argument for higher clock speeds isn't valid either as the highest clock speed on AMD's roadmaps thus far is only 3.2GHz.

Luckily the performance impact of the higher latency L2 cache isn't noticeable in all applications, thanks to the K8's on-die memory controller, but make no mistake - the new core is slower. We couldn't figure out why AMD made the change and with most of our key AMD contacts on vacation due to the holidays, we still have no official response on the matter. Rest assured that if/when we learn more we will let you know.

Updated: AMD has given us the official confirmation that L2 cache latencies have increased, and that it purposefully did so in order to allow for the possibility of moving to larger cache sizes in future parts. AMD stressed that this wasn't a pre-announcement of larger cache parts to come, but rather a preparation should the need be there to move to a vastly larger L2. Thankfully the performance delta isn't huge, at least in the benchmarks that we saw, so AMD's decision isn't too painful - especially as it comes with the benefit of a cooler running core that draws less power; ideally we'd like the best of all worlds but we'll take what we can get. Note that none of AMD's current roadmaps show any larger L2 parts (other than the usual 2x1MB offerings), which tells us one of two things: either AMD has some larger L2 parts that it's planning on releasing or AMD is being completely honest with the public in saying that the larger L2 parts will only be released if necessary.

[PetNorth]

I find it funny if it should be incorrect. Its a very simple and basic test to find out the latency. But again, as gaming benchmark shows. Should and is aint always the same when a 4600(90nm) runs in circles around a 4800(65nm).

http://www.firingsquad.com/hardware/...view/page5.asp

And since K8 is hardly memory bandwidth constrained. Something else leads to this high difference (And obvious mislabeling).

http://www.bit-tech.net/hardware/200...risbane/8.html
http://www.bit-tech.net/hardware/200...risbane/9.html
http://www.bit-tech.net/hardware/200...isbane/10.html

[stealth17]

http://www.anandtech.com/cpuchipsets...spx?i=2893&p=3

Updated - 1/5/07: Although AMD previously did not mention any issues with our findings, we were contacted today and informed that the latency information both ScienceMark and CPU-Z produced is incorrect. The Brisbane core's L2 latency should be 14 cycles, up from 12 cycles and not 20 cycles. This would help explain the relatively low impact on application performance that we've seen across the board. We are still waiting to hear back from AMD on a handful of other issues regarding Brisbane and will update you as soon as we have more information.

The original K8 core, in both 130nm and 90nm flavors, had a 12-cycle L2 cache. With Brisbane, as reported by both CPU-Z and ScienceMark, 65nm K8 now has a 20-cycle L2 cache. Generally speaking you move to a higher latency cache if you're planning on introducing a larger cache size, but a quick glance at AMD's roadmaps doesn't show anything larger than a 1MB L2 per core for the next year. The argument for higher clock speeds isn't valid either as the highest clock speed on AMD's roadmaps thus far is only 3.2GHz.

Luckily the performance impact of the higher latency L2 cache isn't noticeable in all applications, thanks to the K8's on-die memory controller, but make no mistake - the new core is slower. We couldn't figure out why AMD made the change and with most of our key AMD contacts on vacation due to the holidays, we still have no official response on the matter. Rest assured that if/when we learn more we will let you know.

Updated: AMD has given us the official confirmation that L2 cache latencies have increased, and that it purposefully did so in order to allow for the possibility of moving to larger cache sizes in future parts. AMD stressed that this wasn't a pre-announcement of larger cache parts to come, but rather a preparation should the need be there to move to a vastly larger L2. Thankfully the performance delta isn't huge, at least in the benchmarks that we saw, so AMD's decision isn't too painful - especially as it comes with the benefit of a cooler running core that draws less power; ideally we'd like the best of all worlds but we'll take what we can get. Note that none of AMD's current roadmaps show any larger L2 parts (other than the usual 2x1MB offerings), which tells us one of two things: either AMD has some larger L2 parts that it's planning on releasing or AMD is being completely honest with the public in saying that the larger L2 parts will only be released if necessary.

Well this *might* not be such a bad thing after all. I bet that it would help out when trying to overclock with looser latency's. Much like it does with ram. Food for thought anyways.

[Turtle 1]

NN-step . Please show were Z- ram is going to be used on K8l. A link would be nice. I really don't care one way or another but your saying it without facts to back it up = FUD. I think K8l will be a good performing cpu. But this Fud on both sides is stupid.

I just read in news section on the Penryn. were you stated the penrtn was a simple die shrink.

It been reported that Intel is going to add 30 ssee4 additions and it will be High K with metal gates. Thats a bit more than a simple die shrink.

I can get links to support this . It is also stated and I can get links to support it . That yorkfield will have 12mb. of shared cache between all 4 cores. Now I don't know if its true but I can get links to support it.

So all I ask from you is links that support K8L will have Zram. You can supply these links correct.

[doompc]

Turtle 1, Yorkfield will be based on 2 Wolfdale chips, 6MB os cache for 2 cores and another 6MB for the other 2, just like Kentsfield 4+4MB.

Intel's future native quad-core (probably only on next m-architecture Nehalem) will feature about 8MB of L2 cache shared beetwin all cores.

[Turtle 1]

Turtle 1, Yorkfield will be based on 2 Wolfdale chips, 6MB os cache for 2 cores and another 6MB for the other 2, just like Kentsfield 4+4MB.

Intel's future native quad-core (probably only on next m-architecture Nehalem) will feature about 8MB of L2 cache shared beetwin all cores.

As I said I don't know what the trueth is. But I can get links= to any links you have saying otherwise. I am still waiting for any link that says K8L will support Zram.

http://www.xbitlabs.com/news/cpu/dis...930234444.html

http://www.channelregister.co.uk/200...ies_yorkfield/

[ted3]

As I said I don't know what the trueth is. But I can get links= to any links you have saying otherwise. I am still waiting for any link that says K8L will support Zram.

http://www.xbitlabs.com/news/cpu/dis...930234444.html

Would be nice if it were true . The link is dated Sep30-06, early rumor only.
About Zram cache i think some posters here need to moderate themselfes a bit, this thread is getting uncomfortable. And why i dont think k8l will use zram: Why go for so small caches (4x512kB + 2MB) if they master die-space saving ZRAM tech?

[Shadowmage]

I never said that you can't talk about K8L's performance, I said that doing so is much like trying to tell the future by gazing into a crystal ball.

That's not true: you can most definitely figure out K8L's performance by doing some simulations. It won't be exact, but it would be accurate probably within 5-10%. How would you do the simulations? With SimpleScalar, of course

http://www.simplescalar.com/

I'm going to be using SimpleScalar for future projects anyways, so I'll be fiddling around with it. If I get anything interesting I'll report back here. If I get something REALLY interesting watch for a news item :p

[vitaminc]

About Zram cache i think some posters here need to moderate themselfes a bit, this thread is getting uncomfortable. And why i dont think k8l will use zram: Why go for so small caches (4x512kB + 2MB) if they master die-space saving ZRAM tech?

a deep-well doping capacitor in 65nm process using first generation immersion litho is the perfect way for amd to kill its own yield rate.

[Shintai]

Turtle 1, Yorkfield will be based on 2 Wolfdale chips, 6MB os cache for 2 cores and another 6MB for the other 2, just like Kentsfield 4+4MB.

Intel's future native quad-core (probably only on next m-architecture Nehalem) will feature about 8MB of L2 cache shared beetwin all cores.

Thats very unlikely. Since a 12MB cache quadcore yorkfield in die size would only be a tiny bit bigger than a Core 2 Duo 4MB today.

[Flambo]

Shintai,

Are you sure you're not Adam Sternberg?

[largon]

3ns? Thats pretty slow for any type of cache. And just look on the disaster with added latency to the 65nm K8.

Slow?
Yeah right.
K8 L1 access latency at 2.6GHz: 1.15ns (3T)
K8 L2 access latency at 2.6GHz: before RevG: 4.6ns (12T) / RevG1: 5.4ns (14T)

3.0ns doesn't sound too bad now, does it?

The new 3.2Ghz GDDR4 samples (DRAM) got 0.6ns access time. Just to show something to compare with.

Wrong. The chip you mentioned has a cycle time of 0.625ns, that's not the same as access time.

Just the column access strobe for such a GDDR chip ranges from 12T to 21T, yielding 7.5 - 13.75ns just for CAS.
Also, CAS isn't the only step in accessing a RAM chip, thus it will take several dozen nanoseconds before you can go about and w/r anything into/from a RAM chip.

Actually work time? You do know that with 3ns worktime, the read request alone would be 3ns if a single cycle and 400Mhz?

Innovative Silicon (ZRAM pioneer) claims a 3ns r/w latency, meaning it takes only 3ns to prepare the cell for a read/write. Since ZRAM can be accessed in 3ns it obviously is capable of >>400MHz. Otherwise 3ns access time wouldn't make any sense.
And btw, AMD licenced the 2nd gen ZRAM capable of greater freq than 400MHz.

Z-RAM isn’t fast enough to replace SRAM in the L1 caches of microprocessors, but L2 and L3 caches could use it.

-Innovative Silicon Inc.

[Fred_Pohl]

That's not true: you can most definitely figure out K8L's performance by doing some simulations. It won't be exact, but it would be accurate probably within 5-10%. How would you do the simulations? With SimpleScalar, of course

http://www.simplescalar.com/

I'm going to be using SimpleScalar for future projects anyways, so I'll be fiddling around with it. If I get anything interesting I'll report back here. If I get something REALLY interesting watch for a news item :p

Well, when you calculate K8L's overall real-world performance to within 5-10% accuracy, please post your prediction. Then please come back in ~6 months when real K8L benchmarks might be available so you can take a bow or eat your crow.

[Turtle 1]

Well after the Bell next week on tuesday. Well know A lot more. I must say Its not looking Good tho.
HP is Moving ahead of Dell by a large margin. Apple Is gaining Computer market Share. There is a excess of left over PC's from the Xmas buying period.
If K8L was really all that AMD would be talking about it. Ya I know that some will say AMD keeps quite. I say BS.
In Dec . AMD out and out lied to investors about sales. Which caused the Stock to rise. If I was one of tho's investers that bought on that news. I would be sueing for giving out false info. This should be illeagal and those involved should be prosectuted . Just as Margret Stewart was. I don't see where giving out insider info is any worse than putting out false info that secure a loan and cause the stock to rise.

At any rate if AMD is willing to stup to such tactics. IF K8L was all that. AMD would be talking about it.

[nn_step]

Well after the Bell next week on tuesday. Well know A lot more. I must say Its not looking Good tho.
HP is Moving ahead of Dell by a large margin. Apple Is gaining Computer market Share. There is a excess of left over PC's from the Xmas buying period.
If K8L was really all that AMD would be talking about it. Ya I know that some will say AMD keeps quite. I say BS.
In Dec . AMD out and out lied to investors about sales. Which caused the Stock to rise. If I was one of tho's investers that bought on that news. I would be sueing for giving out false info. This should be illeagal and those involved should be prosectuted . Just as Margret Stewart was. I don't see where giving out insider info is any worse than putting out false info that secure a loan and cause the stock to rise.

At any rate if AMD is willing to stup to such tactics. IF K8L was all that. AMD would be talking about it.

1) it was Martha Stewart and that was for insider trading
2) inaccurate predictions are things done by every company even Intel. So please get off your horse

[Turtle 1]

No high horse here that wasn't a prediction it was an out an out lie. The conferance was on the 15 of dec. just 15 days before the end of the qt. AMD new they were lieing . Unless you want us to believe AMD was thinking the last 15 days in DEC were going to the greatest 15 days in the history of cpu sales. IF AMD would have said it befor the qt started I could undestand it. But with 15 days left in the qt. It was an out and out lie. It should also be treated as Fraud. Because thats what it was. They commeted fraud to secure loans. Many investors also bought stock on those comments.

[savantu]

..
2) inaccurate predictions are things done by every company even Intel. So please get off your horse

I say get a clue and actually find how the story unfolded...

Are you implying AMD didn't know how the reality will pan out with 2 weeks to go from that Q ?

They missed their targets by less than 5% when less than 17% of the quarter was left. Which means that missed their targets by about 30% for second half of December. Not only that but inventory skyrocketed in the last part of December altough prices were at an all timelow.So much for the "capacity constrained" AMD. I guess they didn't know that on Dec 15.

http://www.vr-zone.com/?i=4475

[GoThr3k]

if i had the money,i would buy amd shares within a few days, they are really cheap at this moment :p
around 17 and they will rise

[Fred_Pohl]

Good advice, Brent. At least you tried... I still remember being laughed at when I advised selling AMD back in March while it was still around $40. How anyone could have thought that it could go anywhere but down from there eludes me.

[GoThr3k]

I (and most analysts) disagree with this. Until AMD has a product that can compete with Intel on a performance basis, they are going to have to significantly undercut them on price. This is going to hurt margins (more than we saw last quarter) and drive their share price down further.

When K8L comes out I will re-evaluate a large AMD stock purchase, but right now they are projected to settle around the $12-15 range. Buy now and you just ride the wave down.

i know that
just the reason why i would buy amd stock within a few days,it cannot keep up this downward spiral,it will stop getting lower, the most chips are sold in the budget category,not high end
for most people a 3800+ will do
not everyone spends +300€ on a cpu
the move to 65nm improves yields,they just started that transition,amd still sells plenty of chips
i would buy when the share should be around 16$

Good advice, Brent. At least you tried... I still remember being laughed at when I advised selling AMD back in March while it was still around $40. How anyone could have thought that it could go anywhere but down from there eludes me.

your first post i can agree with
i didnt understand why people were buying amd stock at that price