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Thread: A look at Intel's upcoming Sandy Bridge

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    A look at Intel's upcoming Sandy Bridge

    THE RUMORS AND bits about Intel's next generation core, Sandy Bridge, are starting to come out here and there, but several big chunks have still not been outed. Here are a few of them.

    http://www.semiaccurate.com/2010/02/...-sandy-bridge/

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    Typical Charlie BS. A bunch of guesswork basing on pixelated die shot, that is not even confirmed to be genuine.
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    i wasn't sure about the ring bus but when i googled it i came up with this article from 2007 about larrabee http://arstechnica.com/hardware/news...ee-part-ii.ars
    The presentation also includes some details about Intel's 32nm "Gesher" CPU, due out in 2009. In brief, it's 4-8 cores, 4GHz, 7 double-precision FLOPs/cycle (scalar + SSE), 32KB L1 (3 clocks), 512KB L2 (9 clocks), and 2-3MB L3 (33 clocks). The cores are arranged on a ring bus, just like Larrabee's, that transmits 256 bytes/cycle. Gesher is due out sometime in 2009.
    "Gesher" was the former codename for sandybridge.

    that description from '07 has a lot in common with this pic, which is a few months old.
    the GPU "connection" to the l3 must be through the ringbus
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    Last edited by hollo; 02-28-2010 at 07:26 AM.

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    I'm really hoping for a few chips without integrated graphics. Look at the hit in bandwith that we saw with dual core 1156.

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    Quote Originally Posted by BababooeyHTJ View Post
    I'm really hoping for a few chips without integrated graphics. Look at the hit in bandwith that we saw with dual core 1156.
    i3 / i5 with IGP is of a MCM design with traditional CPU + Northbridge

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    I'm really hoping for a few chips without integrated graphics. Look at the hit in bandwith that we saw with dual core 1156
    we shouldn't see that kind of performance hit like with 1156 dualies.
    since the graphics will be integrated on the actual cpu die unlike with
    clarkdale where the IMC is located off the cpu die and put on the 45nm
    graphics die(GMCH) to help with graphics/memory performance.
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    Quote Originally Posted by S|A
    The last bit is something that most people won't think is a big deal, but it is quite possibly the biggest bang of the new chip. Intel is going to rearrange the internal architecture of Sandy to an extent that insiders tell us hasn't really been done since the Pentium Pro back in the middle ages. The precise details are very hazy, but signs point to much greater flexibility, especially in terms of memory operations.
    Hm, interesting... Not sure that is actually true, though. But would be about time!
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    Quote Originally Posted by BababooeyHTJ View Post
    I'm really hoping for a few chips without integrated graphics. Look at the hit in bandwith that we saw with dual core 1156.
    The hit in BW you are referring to has more to do with the fact that the memory controller was placed on the IGP die rather than on the CPU die. Sandybridge will move it back into the same die. (EDIT: Others above beat me to it, did not read all the way through)
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    and also the biggest hit was in latency.
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    Quote Originally Posted by xoqolatl View Post
    Typical Charlie BS. A bunch of guesswork basing on pixelated die shot, that is not even confirmed to be genuine.
    Die shot from IDF 2009
    ?

    ring bus huh? interesting...

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    ring buses are quite terrible for performance. their advantages in terms of wire saving are negated by nasty bottlenecks. remember r600, larrabee?

    revolutionary as ppro? not really especially when talking about flexibility in memory operations. that could only be avx related. the internal architecture only executes the instructions it supports.

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    Quote Originally Posted by JumpingJack View Post
    The hit in BW you are referring to has more to do with the fact that the memory controller was placed on the IGP die rather than on the CPU die. Sandybridge will move it back into the same die. (EDIT: Others above beat me to it, did not read all the way through)
    Thanks, thats kind of what I figured from the die shot but wanted a little reassurance.
    Quote Originally Posted by radaja View Post
    and also the biggest hit was in latency.
    Both from what I saw. The hit in bandwith was just a little less massive than latency. Most of the benches that I saw weren't too far off from my 775 setup in bandwith or latency.

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    Quote Originally Posted by Chumbucket843 View Post
    ring buses are quite terrible for performance. their advantages in terms of wire saving are negated by nasty bottlenecks. remember r600, larrabee?

    revolutionary as ppro? not really especially when talking about flexibility in memory operations. that could only be avx related. the internal architecture only executes the instructions it supports.
    yes, thats what i thought as well...
    and i dont expect any performance wonders from any of the bridges...
    they are just that, bridges from what we have now to where they want to go...
    haswell will be the first chip that steps up performance i think...
    until then its all about saving costs through integration

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    Wow that article had absolutely zero real content....

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    Sandy Bridge R = 2011
    Sandy Bridge B2= 135X(X=>5 <7)
    Sandy Bridge H2= 1155
    Last edited by sxs112; 03-01-2010 at 03:09 PM.

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    Quote Originally Posted by sxs112 View Post
    Sandy Bridge R = 2011
    Sandy Bridge B2= 135X(X=>4 <6)
    Sandy Bridge H2= 1155
    I was told that the H2 will be re tweaked?

    So are they going wth the initial sample or the tweaked one?
    Coming Soon

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    Quote Originally Posted by radaja View Post
    Very hard i dont think so, i was told that the new igp can not be used with 1156 at all.
    Coming Soon

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    Quote Originally Posted by radaja View Post
    I highly doubt that, but it'd be really nice.
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    Quote Originally Posted by radaja View Post
    Most rumours are suggesting s1155m though, which is very different from s1156. I don't think this would be an impossible thing to do, though (look at AMD with Bulldozer and AM3), Intel just won't go for it to make more $...
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    Sandybridge is going to use yet another entirely new socket? Again? Sigh, Intel should learn from AMD on that part. I love the fact their sockets are often backwards compatible. Too bad I'm running an Intel setup myself though

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    would you really want to put your nice new cpu on a 2-4 year old mobo anyway, Every time I have ever changed a cpu the mobo has been changed also.

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    Quote Originally Posted by gallag View Post
    would you really want to put your nice new cpu on a 2-4 year old mobo anyway, every time i have ever changed a cpu the mobo has been changed also.
    werd.

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    Quote Originally Posted by gallag View Post
    would you really want to put your nice new cpu on a 2-4 year old mobo anyway, Every time I have ever changed a cpu the mobo has been changed also.
    My 3.5 years old P5B-Deluxe isn't agree. Works like a charm with Q9550 E0

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