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Thread: AMD Shanghai is officially out

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  1. #1
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    At low speeds yes. At 2.8 and 3Ghz its already 125W TDP again. The new limit just moved abit upwards. But it behaves just as with 65nm. Try a lower clocked 65nm Phenom/Barcelona and you see alot lower power consumption.

    To compare you can buy 3.4 and 3.5Ghz 45nm Xeons.

    1.5V Deneb C1 3.6G Stable air. Deneb C1 uses 1.368V for 3Ghz

    And 1.6V for 3.8Ghz.

    Last edited by Shintai; 11-13-2008 at 11:18 AM.
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  2. #2
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    Quote Originally Posted by Shintai View Post
    At low speeds yes. At 2.8 and 3Ghz its already 125W TDP again. The new limit just moved abit upwards. But it behaves just as with 65nm. Try a lower clocked 65nm Phenom/Barcelona and you see alot lower power consumption.
    Can we just wait for Deneb OCing(for overvolt tests) to see how it actually behaves?Did you miss the toppc report at coolaler forum on Deneb C1 OCing?The dude hit 4.2Ghz on air.For a "leaky" (in your words) part it was doing quite good.
    Also if you missed the Deneb C0 early preview from August,you could see it practically halved the power draw while running at the same measly clock of 2.3Ghz.
    I'm reserving my final judgement on power draw at both stock and OC for a reviews day.
    Quote Originally Posted by Blaber View Post
    Guys this might surprise you but according to Anandtech Deneb has 8MB OF L3 CACHE : http://www.anandtech.com/cpuchipsets...7&p=2#comments

    WTF ; IF ITS TRUE THEN AMD fooled us all
    No it doesn't... The slide says 8 MB of cache but a genius who wrote the article wrote 8MB of L3 cache.It's anandtech...
    Last edited by informal; 11-13-2008 at 11:10 AM.

  3. #3
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    Quote Originally Posted by informal;No it doesn't... The slide says[B
    8 MB of cache[/B] but a genius who wrote the article wrote 8MB of L3 cache.It's anandtech...
    K , so its L2 of 2MB + L3 of 6MB == 8MB , correct ???

  4. #4
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    Quote Originally Posted by Blaber View Post
    K , so its L2 of 2MB + L3 of 6MB == 8MB , correct ???
    Yup, just like Nehalem has 8MB of total usable cache.
    "When in doubt, C-4!" -- Jamie Hyneman

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  5. #5
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    Quote Originally Posted by Shintai View Post
    At low speeds yes. At 2.8 and 3Ghz its already 125W TDP again. The new limit just moved abit upwards. But it behaves just as with 65nm. Try a lower clocked 65nm Phenom/Barcelona and you see alot lower power consumption.

    To compare you can buy 3.4 and 3.5Ghz 45nm Xeons.

    1.5V for 3.6Ghz...

    Are you sure cpu-z is reading volts on cpu correctly ????

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