Lets talk breaking the HTT 230 limit on k10 here

[lukija]

I made a little tool, hope it helps. FIDs are listed in both HEX and DEC values.

@Tony

Are you sure about mappings for NB Multi? Shouldn't it be like this:

00 - 4
01 - 5
02 - 6
...

[Tony]

I made a little tool, hope it helps. FIDs are listed in both HEX and DEC values.

@Tony

Are you sure about mappings for NB Multi? Shouldn't it be like this:

00 - 4
01 - 5
02 - 6
...

Well i was given some insider info and help by an old friend; he did not mention 00 is 4 01 is 5 etc. I will double check.

To all.

I will be receiving a new bios from DFI tomorrow,if i have time i will rename all the hex options to what they are in DEC so its easy to understand.

asus, msi, gigabyte...all have NB multi manipulation being built into bios right now, so things are going to get easier.

thank bingo13, macci and the OP for getting this info into the right hands, we want the boards to work as best they can.

now you have some of the info needed to spot poor reviews you know there will be a few..LOL

[Tony]

Well i was given some insider info and help by an old friend; he did not mention 00 is 4 01 is 5 etc. I will double check.

To all.

I will be receiving a new bios from DFI tomorrow,if i have time i will rename all the hex options to what they are in DEC so its easy to understand.

asus, msi, gigabyte...all have NB multi manipulation being built into bios right now, so things are going to get easier.

thank bingo13, macci and the OP for getting this info into the right hands, we want the boards to work as best they can.

now you have some of the info needed to spot poor reviews you know there will be a few..LOL

I must be blind or something...

does that help?

[lukija]

According to AMD BKDG, page 240

F3xD4 Clock Power/Timing Control 0 Register

4:0 NbFid:

Northbridge frequency ID. Read-write. Cold reset: value varies by product. After a cold reset, this specifies the FID at which the NB is designed to operate. After a warm or cold reset, the NB FID may or may not be reflected in this field, based on the state of NbFidEn. The NB FID may be updated to the value of this field through a warm or cold reset if NbFidEn=1. If that has occurred, then the NB COF is specified by:
• NB COF = 200 MHz * (F3xD4[NbFid] + 4h) / (2^MSRC001_00[68:64][NbDid]).

This field must be programmed to the requirements specified in MSRC001_0071[MaxNbFid] and must be less than or equal to 1Bh, otherwise undefined behavior results. This field must be programmed to the same value for all nodes in the coherent fabric as specified by 2.4.2.6 [BIOS Northbridge COF and VID Configuration] on page 35. See also section 2.4.2 [P-states] on page 31. BIOS must not change the NbFid after enabling the DRAM controller.