AMD to start 45nm ramp in H1 2008

[savantu]

@ Savantu, could you summarize what the article means for AMD? They do have a year (all of 2008) to make that decision and face those challenges, based on which decision they make.
....

Things aren't so simple.

You have 2 main types of leakage in a transistor : gate leakage and subthreshold.

Subthreshold was the bigger one in 130 ,90nm but at 65nm gate leakage took over.SOI helps with subthreshold leakage and a few other things, but has no effect on gate leakage and brings a different set of problems.

The problem : once you get to 65nm and lower gate leakage increases dramatically.As a result , SOI's usefulness in reducing leakage is getting smaller and smaller.Also you can fight subthreshold leakage with circuit design techniques ( does Intel's Restrictive Design Rules ring a bell ? )

How do you fight gate leakage ? With metal gate and high-k dielectrics.These 2 things become a must have for a successful 45nm process.AMD lacks both at the 45nm node AFAIK .Intel virtually pushed back the problem by decreasing gate leakage by a factor of 10.

Now go back to my previous post and reread the comment on SOI problems with carrier mobility degradation and threshold voltage.

Basically it boils down to : AMD is FUBARed if they don't do something fast.Basically they are waiting for IBM to pull their a** out , yet IBM suffers from the same problems.

To give you a hint on AMD's problems , let's look at their 65nm process. Besides the official PR BS with "most advanced , high yields" the process is significantly different from what was expected.

In 2005 when AMD presented their tech papers on their 65nm process they reported a 1.2 nm thick oxide (the same thickness as Intel's 65 nm), yet Semiconductor.com reported (I saw at EETimes) just recently reversed engineered a barcelona chip in which AMD's oxide thickness was actually 25% thicker than Intels.

...The transistor performances of Intel's Woodcrest and AMD's Barcelona appear to match fairly closely, with the Barce- lona's gate leakage about half that of the Woodcrest. This is not so surprising, as Intel uses a 25 percent thinner gate dielectric....

http://www.eetimes.com/news/design/s...leID=202100946


The 65nm node was the 1st process node where gate thickness stayed the same : this was done to keep gate leakage under control.


AMD even increased their oxide thickness from 1.2nm (90nm) to 1.5nm for 65nm in order to keep leakage under control.
Does this help with leakage ? Yes. Does it diminishes transistor performance ? Yes. Basically , their 65nm is excellent power wise , but clocks like sh*t.If you wonder why 65nm K8/K10 can't hit higher clocks , look no further.


But what do you do at 45nm ? Intel didn't bother with SiO2 , say hello to Hafnium which solved the problem , but AMD will have massive problems with oxide thickness/leakage/voltage as they try to hit clocks at 45 nm.

[PhilDoc]

but clocks like sh*t.If you wonder why 65nm K8/K10 can't hit higher clocks , look no further.


.

All of this is pretty much speculation even by the experts. I'm not one of them and none of us probablya are, so I'll just wait and see.

I do know as far as clocking, I've seen a 5000+ hit 3.7G on air and a Barcelona get a 400mhz oveclock with stock votage on air. Maybe the experts were wrong about AMD's abitlity to get higher clocks.

[Hornet331]

All of this is pretty much speculation even by the experts. I'm not one of them and none of us probablya are, so I'll just wait and see.

I do know as far as clocking, I've seen a 5000+ hit 3.7G on air and a Barcelona get a 400mhz oveclock with stock votage on air. Maybe the experts were wrong about AMD's abitlity to get higher clocks.

The discussion is not about the current 65nm parts, its about the upcoming 45nm parts.

Also its nice that amd finaly has masterd its 65nm process, thought it should have been there from the start, not a year later.

[grunge100]

Savantu,

You seem to know alot about soi vs bulk silicon. Do you work for a semiconductor company? You should visit scientias blog and discuss this material there.

[grunge100]

Phildoc,

Savantu said 65nm soi clocks like s**t. I believe him. 3.7Ghz on 65nm-must be fake.

[Shintai]

Phildoc,

Savantu said 65nm soi clocks like s**t. I believe him. 3.7Ghz on 65nm-must be fake.

And compared to competitors it is what?

SOI today is a big bleeding wound on AMD. It was the chance they took. Bulk vs SOI is an easy question for 45nm and down. At 130nm and 90nm it was another ballgame.

I personally dont like AMDs work with IBM on this area. IBM tends to go exotic rather than practical in many cases. And there just aint room for that with a fierce competition. Specially not when you are also with your head down in the mud.

[savantu]

Phildoc,

Savantu said 65nm soi clocks like s**t. I believe him. 3.7Ghz on 65nm-must be fake.

Those 2 things aren't exclusive.

Individual OCs say virtually nothing about what AMD can crank out of the 65nm process.

AMD's 65nm process was optimized for low power , not speed.As a result 65nm K8 isn't able to match 90nm K8 in top frequency , at least not yet( probably never will ) .

As a rule of thumb a shrink is able to do 20% better than the previous process size at the same power.

3-3.2GHz 90nm 125w -> 3.6-3.8GHz 65nm 125w

AMD is stuck at under 2.8GHz.

See more here :

Interestingly, this first application of 65-nm technology was designed not to improve performance over the previous, 90-nm Athlon, but to reduce power consumption.

http://www.eetimes.com/showArticle.j...leID=196701745

The tradeoffs involved in keeping leakage under control = slow transistors speed , difficult to reach higher frequencies.

Dirk Meyer says something interesting :

The issue has been simply one of tuning the design to the technology so as to support a high volume ramp.

IMO , they cover the flaws of the process with the design of the chip , as to minimize them. ( same as Thoroughbred days , they added more layers , etc )

K10 has excellent power usage when running at low speed , once you crank up the speed the power usage goes through the rough ( slower , thicker transistors need more voltage , remember the 1.52V 2.5GHz sample ? ).

[informal]

Those 2 things aren't exclusive.

Individual OCs say virtually nothing about what AMD can crank out of the 65nm process.

AMD's 65nm process was optimized for low power , not speed.As a result 65nm K8 isn't able to match 90nm K8 in top frequency , at least not yet( probably never will ) .

As a rule of thumb a shrink is able to do 20% better than the previous process size at the same power.

3-3.2GHz 90nm 125w -> 3.6-3.8GHz 65nm 125w

AMD is stuck at under 2.8GHz.

See more here :

http://www.eetimes.com/showArticle.j...leID=196701745

The tradeoffs involved in keeping leakage under control = slow transistors speed , difficult to reach higher frequencies.

Dirk Meyer says something interesting :

IMO , they cover the flaws of the process with the design of the chip , as to minimize them. ( same as Thoroughbred days , they added more layers , etc )

K10 has excellent power usage when running at low speed , once you crank up the speed the power usage goes through the rough ( slower , thicker transistors need more voltage , remember the 1.52V 2.5GHz sample ? ).

Savantu,you can't expect that uarchitecture that was originally designed for 90nm process and introed at 130nm to scale up to 3.6-3.8Ghz at 65nm.It isn't only the process that matters,but as D.Mayer recently said (about K10),"wedding the design to the process".
So no,nobody ever expected K8(in X2 variant even less!) to go to 3.6-3.8Ghz ,125W on 65nm process.There are other limitations in K8 that would come into play,it's not the process alone.

[savantu]

Savantu,you can't expect that uarchitecture that was originally designed for 90nm process and introed at 130nm to scale up to 3.6-3.8Ghz at 65nm.It isn't only the process that matters,but as D.Mayer recently said (about K10),"wedding the design to the process".
So no,nobody ever expected K8(in X2 variant even less!) to go to 3.6-3.8Ghz ,125W on 65nm process.There are other limitations in K8 that would come into play,it's not the process alone.

I'm fully aware of that , however ,as ceteris paribus a shrink will offer some frequency gains.
I'm really interested to see what frequency will K10 reach since its pipeline is basically the same as K8.The sudden jump in power consumption from 2.3/2.4GHz to 2.5/2.6GHz is indicative of an inflexion point in the shmoo.