Macro/Micro architectural imporvements of K8L(K10) over K8

[Dresdenboy]

Thanks for all the hype, guys

My original source were these slides:
http://public.cranfield.ac.uk/SOE_te...don_071206.pdf
They also contain a lot of other interesting stuff.

I compiled this list to answer a posting from someone, who seems to deny any IPC improvements in K10's core except for some FP related stuff. Throwing a huge list at him seemed to be a better argument than just saying ("It has improvements"). This was a good motivation And don't forget my comment:

However, regarding IPC.. Have a look at this list and think about the design efforts and if they'd be worth it, if most of the more general changes wouldn't cause IPC improvements of ~1% or more per core modification?

This thought was my reason for assuming, that we'll see significant IPC improvements on any code (INT/FP) over K8.

The L1 sizes are still 64kB as confirmed by AMD:

At our last phone call, Damon Muzny repeated this at least 3 times that the figure with Data cache might have confused a lot of people: but the L1 is still 64KB D + 64 KB I, just like it was before.

http://aceshardware.com/forums/read_...8309&forumid=1
This has been discussed months ago and BTW the die plot's have never shown smaller L1 caches.

The clock gating stuff now officially confirmed by AMD first appeared in Yager's heavily critized article on computerworld. My take on this was:

First I didn't read the full article (because it sounded like simple PR), but then I saw this sentence quoted above. If that is true, then (and probably together with an Intelish typ. TDP) AMD would really yield more sellable parts and could maybe even offer HE variants right from start.

I wrote about AMD's patents regarding such fine grained power saving a while ago. Interestingly the 2 inventors (Filippo, Pickett) involved in power saving stuff are well known names on many other patents (like Pat. No. 7,165,167, where you'll find both together with Ben "Barcelona Man" Sander), which fit nicely to Barcelona's new features. So for the interested ones:

Pat. No. 6,826,704 - Microprocessor employing a performance throttling mechanism for power management
Pat. No. 6,983,389 - Clock control of functional units in an integrated circuit based on monitoring unit signals to predict inactivity
Pat. No. 6,976,182 - Apparatus and method for decreasing power consumption in an integrated circuit

And again the filing dates of most of these patents (2002/2003) should make clear, that Barcelona is not an answer to Intels new architecture. People knowing the design lifecycle of such a highly integrated CPU never thought so.

(http://www.siliconinvestor.com/readm...msgid=23261707)

If AMD is really going to use Intelish TDP numbers (based on measurements while running some "power virus" software) and as it has these HW based p-state transitions, clock gating and maybe some form throttling, it may increase Barcelona's yield, because they can sell parts, which'll never break the given TDP, while without this power related stuff would have exceeded the currently used TDP "thermal envelope".

AMD's patents show a lot of interesting details regarding K10, like clock gating, details of a 128 bit wide operating FPU (Pat. No. 6,944,744), the new memory controller (e.g. patents about reducing page conflicts), zonal monitoring of temperature on the die, HW based power state transitions, thermal throttling etc.

So it's never bad to have a look at them. BTW, some of the patents by guys, who seem to be K10 architects, are trace cache related.